13 ms·
If you look at a Zen5 die shots half of the space is taken by L3 cache. And from each individual core: - 25% per core L1/L2 cache - 25% vector stuff (SSE, AV
by dist-epoch 1y ago
If you look at a Zen5 die shots half of the space is taken by L3 cache.
And from each individual core:
- 25% per core L1/L2 cache
- 25% vector stuff (SSE, AVX, ...)
- from the remaining 50% only about 20% is doing instruction decoding
https://www.techpowerup.com/img/AFnVIoGFWSCE6YXO.jpg https://www.techpowerup.com/img/AFnVIoGFWSCE6YXO.jpg
- zozbot234 1y agoThe real issue with complex insn decoding is that it's hard to make the decode stage wider and at some point this will limit the usefulness of a bigger chip. For instance, AArch64 chips tend to have wider decode than their close x86_64 equivalents.