This is pretty cool. There were some LFSR-PC CPUs back in the 70s such as the TMS 1000 used in the Speak&Spell https://github.com/mikeakohn/tms1000_fpga https

This is pretty cool. There were some LFSR-PC CPUs back in the 70s such as the TMS 1000 used in the Speak&Spell https://github.com/mikeakohn/tms1000_fpga https://github.com/mikeakohn/tms1000_fpga (its Data Manual omits mention of this, but the Programmer's Reference Manual does mention it https://ia800306.us.archive.org/27/items/bitsavers_tiTMS1000T_10154027/TMS1000pgmRef_1975_text.pdf#page=26 https://ia800306.us.archive.org/27/items/bitsavers_tiTMS1000...), and of course the Atari 2600 TIA raster generator is famous for using an LFSR counter for horizontal position. Ken Shirriff has also documented the use of an LFSR counter for tone generation in the UM66T greeting-card music chip http://www.righto.com/2021/12/reverse-engineering-tiny-1980s-chip.html?m=1 http://www.righto.com/2021/12/reverse-engineering-tiny-1980s... and for Pentium self-test circuitry http://www.righto.com/2025/01/pentium-carry-lookahead-reverse-engineered.html?m=1 http://www.righto.com/2025/01/pentium-carry-lookahead-revers... and for DTMF tone generation. It occurred to me recently that an LFSR-pc CPU could avoid having an address field in its conditional jump instructions, instead doing something like complementing a PC bit. There have been conventional counter-based CPUs that did something like this: Data General's NOVA and HP's RPN calculators had conditional-skip instructions which would skip over the next instruction without executing it if the condition was false. But it was usually a jump instruction, so it didn't really save you space. (The TMS 1000's conditionals also worked this way, but could only skip branch and call instructions.) By contrast, in an LFSR, complementing a bit or incrementing the value takes you potentially far away in the address sequence. The assembler might have to insert NOPs to resolve the occasional collision. The TMS 1000 program counter had an additional twist: it was only 6 bits, but to enable programs of more than 64 instructions, there were multiple 64-byte "pages" of ROM. The page address register was potentially updated on branches, calls, and returns, but not for normal program sequencing. I'm not sure if this actually saved any transistors, but it meant that normal branch instructions only needed a 6-bit field. An additional "load page buffer" instruction was needed for far jumps and calls, and the page buffer register remained loaded with the return page until the return instruction. (Subroutine calls within subroutines were not supported.) https://electronics.stackexchange.com/questions/186762/first-chip-with-1000-or-more-transistors https://electronics.stackexchange.com/questions/186762/first... claims that the TMS 1000 had 8000 transistors, which seems really inefficient compared to things like the 4004 and the MuP21.