5 ms·
You'd need an insanely big FPGA for this.
by saagarjha 1y ago
You'd need an insanely big FPGA for this.
- mikewarot 1y agoThanks to gigabit SERDES links, it should be reasonably easy to send the vectors between chips if you need to distribute the work to fit available FPGA hardware. Note this could also be done if you're just emulating a systolic array on cheap hardware, like Raspberry pi picos, using the built-in PIOs to handle the much lower signal rates.
- saagarjha 1y agoGigabit is incredibly slow for training