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I would LOVE to see an LLM trained simultaneously with ASICs optimized to run it. Or at least an FPGA design.
by UltraSane 1y ago
I would LOVE to see an LLM trained simultaneously with ASICs optimized to run it. Or at least an FPGA design.
- lawlessone 1y agoI think that's basically what nvidia and their competitor AI chips do now?
- UltraSane 1y agoThey use machine learning to optimize general purpose chips. I am proposing that you would train an LLM AND the ultra-optimized hardware that can only run that LLM at the same time. So the LLM and the Verilog design of the hardware to run it would be the output of the training
- jalk 1y agoCan't find the reference now, but remember reading an article on evolving FPGA designs. The found optimum however only worked on the specific FPGA it was evolved on, since the algo had started to use some out-of-spec "features" of the specific chip. Obviously that can be fixed with proper constraints, but seems like a trap that could be stepped into again - i.e. the LLM is now really fast but only on GPUs that come from the same batch of wafers.
- jecel 1y agohttps://www.researchgate.net/publication/2737441_An_Evolved_Circuit_Intrinsic_in_Silicon_Entwined_With_Physics https://www.researchgate.net/publication/2737441_An_Evolved_...