5 ms·
ChatGPT-4o is scary good at writing VHDL. Using it to prototype some low level controllers today, as a matter of fact!
by cushychicken 1y ago
ChatGPT-4o is scary good at writing VHDL.
Using it to prototype some low level controllers today, as a matter of fact!
- roflyear 1y agoIt's better-than-senior at a some things, but worse-than-junior at a lot of things.
- quantadev 1y agoIt's more like better-than-senior 99% of the time. Makes mistakes 1% of the time. Most of the 'bad results' I've seen people struggle with ended up being the fault of the human, in the form of horrible context given to the AI or else ambiguous or otherwise flawed prompts. Any skilled developer with a decade of experience can write prompts that return back precisely what we wanted almost every single time. I do it all day long. "Claude 4" rarely messes up.
- cushychicken 1y agoSame!
- UncleOxidant 1y agoClaude and Gemini are decent at it as well. I was surprised when I asked claude (and this was several months back) to come up with a testbench for some very old, poorly documented verilog. It did a very decent job for a first-cut testbench. It even collected common, recurring code into verilog tasks (functions) which really surprised me at the time.
- cushychicken 1y agoYes! It’s much better at using functional logic than I am - which I appreciate!
- Panzer04 1y agoWhat kind of things is it doing? I have a hard time imagining an LLM being able to do arbitrary things. It always feels like LLMs can do lots of the easy stuff, but if they can't do everything you need the skilled engineer anyway, who'd knock the easy things out in a week anyway.
- cushychicken 1y agoWhat kind of things is it doing? Wrote me: - a SPI deserializer that sets a bit after 12 bits read in, to trigger a prefetch - an SDC constraints file for the deserializer that correctly identified the SPI clock and bus clock as separate domains requiring their own statement - a test bench that validated both that the prefetch bit was being set, and that it was being set at the proper time relative to the SPI clock - a makefile with commands for build, headless test, and debug by loading the VCD into a waveform viewer It always feels like LLMs can do lots of the easy stuff, but if they can't do everything you need the skilled engineer anyway, who'd knock the easy things out in a week anyway. Nearly every part of the tool flow I just described, I would consider “tricky to get right”. Been doing this for ~15 years and it’s still tough to bootstrap something like this from scratch. ChatGPT-4o did this for me from zero in about 15 minutes. I won’t lie: I love it. I can focus on the actual, bigger problems at hand, and not the tricky little details of HDLs. People are either deluding themselves or ignorant of the capabilities of frontier models if they don’t believe LLMs offer a speedup in workflow. I personally believe that most of the doubt and cynicism is due to: 1) a pretty big collective identity crisis among software professionals, and 2) a suspicion that LLMs make it so that anyone who is good at articulating the problem precisely no longer needs a software engineer as a translation specialist from specs to code. I say this as an EE of ~15 years who’s always been able to articulate what I want, specifically, to a firmware counterpart, who then writes the code I need. I can turn years of practice in this skill into great prompts for an LLM, which effectively cuts out the middleman. I really like it. It’s helped me take on a lot of projects that are just outside of my innate level of capability. It’s also helped me learn a lot of new things about these new software adjacent areas. ChatGPT is a great tutor!
- zahlman 1y ago