3 ms·

RISC-V is absolutely not and never has been 'aimed at low power / embedded'. Literally from the very beginning the target was 'be an ISA for everything'. Its ju

RISC-V is absolutely not and never has been 'aimed at low power / embedded'. Literally from the very beginning the target was 'be an ISA for everything'. Its just natural that simpler things were standardized first and came to market first. That POWER is better at top of the market is highly questionable, every new startup coming into the high performance space has universally picked RISC-V over OpenPOWER. Also, nowadays even complex ISA were fine for embedded. The cost difference for stuff like that is tiny. Its really just about how many options do you have in the market, both open and closed. And that's where RISC-V by now simply has more. OpenPOWER was only fake open for a long time, while marketing itself as open. Only when they were totally getting crushed, did they update and are more like RISC-V, but it was many years to late.

bhouston 1y ago
> Its just natural that simpler things were standardized first and came to market first. Which isn't that different than what I am saying. RISC-V is marketing towards low-power/embedded right now because it doesn't have performant cores. https://benhouston3d.com/blog/risc-v-in-2024-is-slow https://benhouston3d.com/blog/risc-v-in-2024-is-slow Power ISA was not focused on this market, its historical market was high performance computing.
- dragontamer 1y ago
  Freescale PowerQUICC fans say whaaaaaat? Power ISA absolutely was used in embedded contexts for years. Decades even. --------- Instruction sets aren't very important actually. Like yeah, compiler infrastructure helps but a lot of embedded decision making is about peripherals. PowerQUICC had powerful and extendable I/O that could be customized to many different needs. And I believe the bulk of those benefits stay over to the updated ARM chip QorIQ (as NXP bought FreeScale and seems to have prioritized ARM).
  - adrian_b 1y ago
    After Motorola has abandoned totally (MC88k, M.core) or partially (MC68k => Coldfire) its older ISAs and it has transitioned to using the POWER/PowerPC ISA, it has applied it to the market in which they was interested, designing many kinds of microcontrollers with it, mainly for the automotive and communications markets, where microcontrollers with higher performance were required. Around the same time IBM has also introduced a series of microcontrollers based on the POWER ISA (PowerPC 4xx). However, when the POWER ISA has initially been designed, before its launch in 1990, its target were high-end scientific workstations and servers made by IBM. The idea of using it in embedded computers has come much later, when the increased density achievable in integrated circuits has made that possible.
    - dragontamer 1y ago
      Sure. But the embedded PowerQUICC chips were in use between the years 199x and 201x, and are still manufactured today in 2025. My overall point is that Power ISA has a long history as both high performance compute AND embedded (be it industrial, automotive, or space embedded). Maybe in the late 1980s POWER was high performance only. But there's a big history here and it's weird to see this discussion ignore Power ISA's long embedded history. ------- Does OpenPower have a chance today? I dunno. Obviously the hype is in RISC-V and maybe a bit of ARM. But it's not a bad ISA and Power used to target embedded not very long ago
adrian_b 1y ago
RISC-V has obviously been initially designed with the only purpose of being extremely simple to implement, simple enough to be implementable by students. Nothing else can justify the weird choices made in designing RISC-V. The idea to use RISC-V in actually useful devices must have come only after the initial design and for this purpose the only advantage of RISC-V versus designing some proprietary CPU core is that for RISC-V there already exists a significant amount of tools for software development, i.e. linkers, assemblers, compilers, debuggers, a few optimized libraries etc. This advantage of RISC-V is extremely important, because developing compilers and all the other required software tools for any new ISA requires much more work and resources than the hardware design of a CPU core implementing it. However, it is sad that the first ISA with a permissive license allowing it to be used by everyone everywhere has been one so bad as RISC-V. It is absurd to claim that the target of RISC-V is to 'be an ISA for everything', when it does not even have adequate means for detecting integer overflow, a feature that existed even in much smaller ancient 8-bit microprocessors, like Motorola MC6800 (1974) and Zilog Z80 (1976). Startups choose RISC-V because it is a fashionable buzzword good for pleasing possible investors and because their team does not include anyone with experience in low-level assembly programming or compiler back-end implementation, the only people who can assess the quality of an ISA.
- Footpost 1y ago
  The reasoning for this choice in the base ISA is discussed in the RISCV ISA manual, Section 2.4 on "Integer Computational Instructions" [1]. Given that RISCV is a modular ISA, it should be possible in principle to have suitable ISA extensions that do integer overflow detection. Maybe the absence of such an extension in 2025 indicates that this is not a pressing need for many RISC-V users? [1] https://lists.riscv.org/g/tech-unprivileged/attachment/535/0/unpriv-isa-asciidoc.pdf https://lists.riscv.org/g/tech-unprivileged/attachment/535/0...
  - snvzz 1y ago
    While very convenient to quickly link some ancient draft spec, let's try and stick to the actual ratified specifications[0]. Of course, the rationale is still there in section 2.4 of the current (20250508) ratified version of The RISC-V Instruction Set Manual Volume I: Unprivileged ISA. 0. https://riscv.org/specifications/ratified/ https://riscv.org/specifications/ratified/

bhouston 1y ago

> Its just natural that simpler things were standardized first and came to market first. Which isn't that different than what I am saying. RISC-V is marketing towards low-power/embedded right now because it doesn't have performant cores. https://benhouston3d.com/blog/risc-v-in-2024-is-slow https://benhouston3d.com/blog/risc-v-in-2024-is-slow Power ISA was not focused on this market, its historical market was high performance computing.

dragontamer 1y ago
Freescale PowerQUICC fans say whaaaaaat? Power ISA absolutely was used in embedded contexts for years. Decades even. --------- Instruction sets aren't very important actually. Like yeah, compiler infrastructure helps but a lot of embedded decision making is about peripherals. PowerQUICC had powerful and extendable I/O that could be customized to many different needs. And I believe the bulk of those benefits stay over to the updated ARM chip QorIQ (as NXP bought FreeScale and seems to have prioritized ARM).
- adrian_b 1y ago
  After Motorola has abandoned totally (MC88k, M.core) or partially (MC68k => Coldfire) its older ISAs and it has transitioned to using the POWER/PowerPC ISA, it has applied it to the market in which they was interested, designing many kinds of microcontrollers with it, mainly for the automotive and communications markets, where microcontrollers with higher performance were required. Around the same time IBM has also introduced a series of microcontrollers based on the POWER ISA (PowerPC 4xx). However, when the POWER ISA has initially been designed, before its launch in 1990, its target were high-end scientific workstations and servers made by IBM. The idea of using it in embedded computers has come much later, when the increased density achievable in integrated circuits has made that possible.
  - dragontamer 1y ago
    Sure. But the embedded PowerQUICC chips were in use between the years 199x and 201x, and are still manufactured today in 2025. My overall point is that Power ISA has a long history as both high performance compute AND embedded (be it industrial, automotive, or space embedded). Maybe in the late 1980s POWER was high performance only. But there's a big history here and it's weird to see this discussion ignore Power ISA's long embedded history. ------- Does OpenPower have a chance today? I dunno. Obviously the hype is in RISC-V and maybe a bit of ARM. But it's not a bad ISA and Power used to target embedded not very long ago

adrian_b 1y ago

RISC-V has obviously been initially designed with the only purpose of being extremely simple to implement, simple enough to be implementable by students. Nothing else can justify the weird choices made in designing RISC-V. The idea to use RISC-V in actually useful devices must have come only after the initial design and for this purpose the only advantage of RISC-V versus designing some proprietary CPU core is that for RISC-V there already exists a significant amount of tools for software development, i.e. linkers, assemblers, compilers, debuggers, a few optimized libraries etc. This advantage of RISC-V is extremely important, because developing compilers and all the other required software tools for any new ISA requires much more work and resources than the hardware design of a CPU core implementing it. However, it is sad that the first ISA with a permissive license allowing it to be used by everyone everywhere has been one so bad as RISC-V. It is absurd to claim that the target of RISC-V is to 'be an ISA for everything', when it does not even have adequate means for detecting integer overflow, a feature that existed even in much smaller ancient 8-bit microprocessors, like Motorola MC6800 (1974) and Zilog Z80 (1976). Startups choose RISC-V because it is a fashionable buzzword good for pleasing possible investors and because their team does not include anyone with experience in low-level assembly programming or compiler back-end implementation, the only people who can assess the quality of an ISA.

Footpost 1y ago
The reasoning for this choice in the base ISA is discussed in the RISCV ISA manual, Section 2.4 on "Integer Computational Instructions" [1]. Given that RISCV is a modular ISA, it should be possible in principle to have suitable ISA extensions that do integer overflow detection. Maybe the absence of such an extension in 2025 indicates that this is not a pressing need for many RISC-V users? [1] https://lists.riscv.org/g/tech-unprivileged/attachment/535/0/unpriv-isa-asciidoc.pdf https://lists.riscv.org/g/tech-unprivileged/attachment/535/0...
- snvzz 1y ago
  While very convenient to quickly link some ancient draft spec, let's try and stick to the actual ratified specifications[0]. Of course, the rationale is still there in section 2.4 of the current (20250508) ratified version of The RISC-V Instruction Set Manual Volume I: Unprivileged ISA. 0. https://riscv.org/specifications/ratified/ https://riscv.org/specifications/ratified/