AFAIK, the relaxed memory models are mostly from processors using pipelined execution and out of order execution. Cache has little to do with it as most modern

AFAIK, the relaxed memory models are mostly from processors using pipelined execution and out of order execution. Cache has little to do with it as most modern processors have transparent cache, meaning you can't tell it there except for performance effects. Differences in memory accesses due to cache state might exacerbate some race conditions but those race conditions would still be there, cache or no cache.