When debugging/fixing timing problems, or trying to implement a functional change using only metal layers - yes, it is absolutely still necessary to debug veri

When debugging/fixing timing problems, or trying to implement a functional change using only metal layers - yes, it is absolutely still necessary to debug verilog at the gate level. Also, "just a tooling issue" is a pretty big problem when you're talking about something that wants to be adopted as part of the toolchain.