4 ms·
Nice work. Just a comment: ADC clock is very sensitive to capacitive loading of the probe as it cannot drive that large load, it most likely fails to generate e
by bgnn 1y ago
Nice work. Just a comment: ADC clock is very sensitive to capacitive loading of the probe as it cannot drive that large load, it most likely fails to generate enough signal swing. It's not advisable to probe clock signals like that.
- tverbeure 1y agoBut probing the ADC clock didn't impact the clock signal itself, only the ADC input signal. How does that happen? FWIW: the clock signal starts at one side of that large PCB and travels to all 4 ADCs, so it must have a serious driver on it.
- deleted 1y ago[deleted]