Very cool. There's a similar project, Polyphony (https://github.com/polyphony-dev/polyphony https://github.com/polyphony-dev/polyphony) that translates Python d

Very cool. There's a similar project, Polyphony (https://github.com/polyphony-dev/polyphony https://github.com/polyphony-dev/polyphony) that translates Python directly into Verilog - no processor (A bit like what HLS does for C++). As part of my degree dissertation I tacked on AXI bus support to it to facilitate communication between the CPU and FPGA on a Zynq as a PoC of doing hardware/software co-design with Python. I'd definitely be interested in how this project progresses, particularly if it adds support for integration to the CPU. Some tie-in to the Pynq project could be super fun.