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I don't get why they decided to create all these very complicated extensions before even getting solid hardware for the base instruction set. RVV support is man

I don't get why they decided to create all these very complicated extensions before even getting solid hardware for the base instruction set. RVV support is many, many years into the future and I bet many of its instructions will be micro coded since they aren't very useful for compilers anyway. Specifying standards for the future before you have working prototypes is very (ahaha) risky.

beej71 2y ago
I can only speculate that the base was insufficient for high commercial traction.
panick21_ 2y ago
There is solid hardware, it just not standard hardware for consumers. RVV support in software is already good and there are already many commercial chips. > I bet many of its instructions will be micro coded since they aren't very useful for compilers anyway I have listened to a lot of the talks about RISC-V and many about Vector extension, and micro-coding was barley mentioned. What is more common is that people don't implement all the instructions in academic settings. > Specifying standards for the future before you have working prototypes is very (ahaha) risky. Absolutely nothing is standardized before hardware implementations exist. In fact, for Vector there was a first generation of the 0.7 that saw limited commercial use and far more more for the RVV 1.0 version.
- bjourne 2y ago
  I looked at RISC-V SoCs last year and I couldn't find anything at all with support for RVV. Just a lot of "coming soon", "in progress", and "preorder now". Maybe the situation has improved since then.
  - brucehoult 2y ago
    When last year? The CanMV-K230 has RVV 1.0 and shipped in November 2023, just two years after RVV 1.0 was ratified. So "nothing at all" was already false before January 1 last year. The BPI-F3 (8x X60 cores with 256 bit VLEN RVV 1.0) was announced in February 2024 and shipped in May. The Lichee Pi 3A and Milk-V Jupiter with the same SoC were not far behind it, and the MuseBook and DC-Roma II laptops were not far behind them. We now also have the Orange Pi RV2 with the same SoC for $30 (2 GB RAM) to $50 (8 GB) It's probably going to be a while before we see the next generation but there are half a dozen different machines available with the current best mass-production RVV 1.0 chip.
brucehoult 2y ago
so completely the opposite complaint than https://news.ycombinator.com/item?id=43762141 https://news.ycombinator.com/item?id=43762141 which said RISC-V people should have skipped all the intermediate implementations and gone straight to x86-competitive competitive high performance cores. i.e. they're probably doing something right. When was the last successful and surviving today brand new ISA released that didn't offer backward compatibility with something that was already big in the market? Not Aarch64 -- it coexisted with 32 bit Arm in all of Arm's cores from 2012 until 2023. Not x86_64 which even to this days runs 32 bit (and 16 bit?) x86 code. MIPS and SPARC are both gone, Alpha and Itanium were never huge and anyway are gone. I guess IBM POWER, originally released as RS/6000 in 1990, 35 years ago. It had design lineage from 801/ROMP, but was not compatible with them.

beej71 2y ago

I can only speculate that the base was insufficient for high commercial traction.

panick21_ 2y ago

There is solid hardware, it just not standard hardware for consumers. RVV support in software is already good and there are already many commercial chips. > I bet many of its instructions will be micro coded since they aren't very useful for compilers anyway I have listened to a lot of the talks about RISC-V and many about Vector extension, and micro-coding was barley mentioned. What is more common is that people don't implement all the instructions in academic settings. > Specifying standards for the future before you have working prototypes is very (ahaha) risky. Absolutely nothing is standardized before hardware implementations exist. In fact, for Vector there was a first generation of the 0.7 that saw limited commercial use and far more more for the RVV 1.0 version.

bjourne 2y ago
I looked at RISC-V SoCs last year and I couldn't find anything at all with support for RVV. Just a lot of "coming soon", "in progress", and "preorder now". Maybe the situation has improved since then.
- brucehoult 2y ago
  When last year? The CanMV-K230 has RVV 1.0 and shipped in November 2023, just two years after RVV 1.0 was ratified. So "nothing at all" was already false before January 1 last year. The BPI-F3 (8x X60 cores with 256 bit VLEN RVV 1.0) was announced in February 2024 and shipped in May. The Lichee Pi 3A and Milk-V Jupiter with the same SoC were not far behind it, and the MuseBook and DC-Roma II laptops were not far behind them. We now also have the Orange Pi RV2 with the same SoC for $30 (2 GB RAM) to $50 (8 GB) It's probably going to be a while before we see the next generation but there are half a dozen different machines available with the current best mass-production RVV 1.0 chip.

brucehoult 2y ago

so completely the opposite complaint than https://news.ycombinator.com/item?id=43762141 https://news.ycombinator.com/item?id=43762141 which said RISC-V people should have skipped all the intermediate implementations and gone straight to x86-competitive competitive high performance cores. i.e. they're probably doing something right. When was the last successful and surviving today brand new ISA released that didn't offer backward compatibility with something that was already big in the market? Not Aarch64 -- it coexisted with 32 bit Arm in all of Arm's cores from 2012 until 2023. Not x86_64 which even to this days runs 32 bit (and 16 bit?) x86 code. MIPS and SPARC are both gone, Alpha and Itanium were never huge and anyway are gone. I guess IBM POWER, originally released as RS/6000 in 1990, 35 years ago. It had design lineage from 801/ROMP, but was not compatible with them.