4 ms·

I'm not aware of any chips, even in development, that will genuinely have full RVA23 support. If you'll settle for "near enough" then my betting is we'll have

by rwmj 2y ago

I'm not aware of any chips, even in development, that will genuinely have full RVA23 support. If you'll settle for "near enough" then my betting is we'll have SiFive P650/P670 hardware first (https://www.sifive.com/cores/performance-p650-670 https://www.sifive.com/cores/performance-p650-670). There are some other development boards coming (sorry, under NDA!) that should have near-RVA23 + Xeon-like performance and we should get them in very end 2025 / early 2026. These are server-class parts so the development boards will not be cheap. Some parts of RVA23 like a complete implementation of the vector sub-extensions, and hypervisor support, are pretty complex.[1] If you just want RVA23 now (with poor performance) then qemu implements it. We found it's not very useful for software development, not just because it's slow, but also because it performs so differently from the real hardware, so you cannot, for example, optimize your vectorized code. [1] I wrote a general article about RISC-V extensions last year: https://research.redhat.com/blog/article/risc-v-extensions-whats-available-and-how-to-find-it/ https://research.redhat.com/blog/article/risc-v-extensions-w...

pantalaimon 2y ago
> There are some other development boards coming (sorry, under NDA!) that should have near-RVA23 + Xeon-like performance and we should get them in 2026. These are server-class parts so the development boards will not be cheap. I can get a 3A6000 system for 400€ with decent (~Zen2) performance, are we talking more than that?
- rwmj 2y ago
  [deleted - didn't realise you were talking about loongarch, see reply below]
  - pantalaimon 2y ago
    But RISC-V predates loongarch64 - why did Loongson create a new ISA instead of implementing a fast RISC-V core? Sure you can move faster if you can make your own standards and don't have to coordinate with anyone, but still makes me wonder if there is some fundamental issue that makes it difficult to create a high performance RISC-V implementation.
    - rwmj 2y ago
      How does it compare to the current RISC-V leader, ESWIN SiFive P550? Anyway, China seem to have decided to pursue a dual strategy of pouring money into RISC-V and LoongArch at the same time. I've no idea why that is. The company I work for talks to several RISC-V vendors who don't believe there is any issue with the RISC-V ISA for high performance server-class application cores.
      - pantalaimon 2y ago
        > How does it compare to the current RISC-V leader, ESWIN SiFive P550? I couldn't find many benchmarks of the P550, but at Phoronix it got beaten by a Raspberry Pi 4 https://www.phoronix.com/review/sifive-hifive-premier-p550 https://www.phoronix.com/review/sifive-hifive-premier-p550 which the 3A6000 beats easiely https://openbenchmarking.org/vs/Processor/Loongson-3A6000,ARMv8+Cortex-A72+4-Core https://openbenchmarking.org/vs/Processor/Loongson-3A6000,AR...
      - adgjlsfhk1 2y ago
        The P550 is pretty slow. It doesn't have any SIMD, and it's scalar engine is ~about the same as a Core 2 from ~2008. In general, it's fairly confusing to me why SciFive has been so cautious in their designs. It seems like they would be in a much better place if they'd released a few CPUs where rather than trying to balance everything while creeping complexity up, they just added all the power to theoretically match high end CPUs and then addressed the bottlenecks over iterations.
        brucehoult 2y ago
        > The P550 is pretty slow. It doesn't have any SIMD, and it's scalar engine is ~about the same as a Core 2 from ~2008. Yes! And this is great progress in just a couple of years. The previous SiFive core that made it to available hardware, the U74, is about like a Pentium or PowerPC 603 in µarch, though with higher clock speed so putting it more like late Pentium 3 or PowerPC G4 in delivered performance (and also quad core, not single core, which helps a lot). SiFive already have 2 1/2 generations of core released since the P550 in mid 2021, the P670 and the P870(-D). Both of those implement RVV (Vector). If not for US sanctions we'd be seeing very nice 16x P670 machines this year, likely quite a bit better than the Pi 5 (and Rock 5 and Orange Pi 5). Or somewhere between Sandy Bridge and Skylake in Intel terms, I think. The P870 is somewhere around Snapdragon 8 gen 2. It just takes time to get CPU cores from the drawing board to shops, and especially for a company that wants to make consumer products to license the core in the first place since SiFive (like Arm) doesn't make chips. RISC-V is behind Arm, but the gap in cores available to license is far smaller (about 2 years at present) than the gap in things anyone can buy in a shop (about 5 years at present) and getting smaller all the time. > it's fairly confusing to me why SciFive has been so cautious in their designs. It seems like they would be in a much better place if they'd released a few CPUs where rather than trying to balance everything while creeping complexity up, they just added all the power to theoretically match high end CPUs Because most of the market (by volume / revenue / profit) does not need the highest end CPUs. Even in phones the Galaxy S25, with its Qualcomm Oryon cores, is a nice headline product, but there are still new SoCs and phones being introduced today (or at least there were some in February 2024 ... I haven't checked recently) with nothing faster than Arm A53 cores announced in 2012. I expect those low end phones are still selling in pretty big numbers.
acka 2y ago
It is a sad day in history to see both a RISC-V-related acronym and NDA used in the same sentence. The term oxymoron barely cuts it IMO. I thought that RISC-V used to stand for open hardware and freedom, TIL.
- boredatoms 2y ago
  Riscv is an open ISA specification, not implementation Organizations are free to make closed and even secret implementations of it if they like
  - ksec 2y ago
    That was not what the RISC-V supporters promised.
    - snvzz 2y ago
      Most "RISC-V supporter" do at the very least understand what RISC-V is, and what it isn't. I have never seen an actual RISC-V supporter confuse ISA and microarchitecture.
    - boredatoms 2y ago
      Who/where are those people, because they seem very misinformed
- rwmj 2y ago
  The RISC-V specs are all free to download and implement. Some (by no means all) implementations are proprietary. Red Hat (the company I work for) talks to all sorts of server vendors, x86, Arm, POWER, RISC-V all the time under NDA so we can find out what new products those vendors are developing before they are released, and have software ready in time. The software we write is all open sourced. This is nothing particular to do with RISC-V, and has nothing to do with the RISC-V ISA, nor with open sourcing of software.

by rwmj 2y ago

pantalaimon 2y ago

> There are some other development boards coming (sorry, under NDA!) that should have near-RVA23 + Xeon-like performance and we should get them in 2026. These are server-class parts so the development boards will not be cheap. I can get a 3A6000 system for 400€ with decent (~Zen2) performance, are we talking more than that?

rwmj 2y ago
[deleted - didn't realise you were talking about loongarch, see reply below]
- pantalaimon 2y ago
  But RISC-V predates loongarch64 - why did Loongson create a new ISA instead of implementing a fast RISC-V core? Sure you can move faster if you can make your own standards and don't have to coordinate with anyone, but still makes me wonder if there is some fundamental issue that makes it difficult to create a high performance RISC-V implementation.
  - rwmj 2y ago
    How does it compare to the current RISC-V leader, ESWIN SiFive P550? Anyway, China seem to have decided to pursue a dual strategy of pouring money into RISC-V and LoongArch at the same time. I've no idea why that is. The company I work for talks to several RISC-V vendors who don't believe there is any issue with the RISC-V ISA for high performance server-class application cores.
    - pantalaimon 2y ago
      > How does it compare to the current RISC-V leader, ESWIN SiFive P550? I couldn't find many benchmarks of the P550, but at Phoronix it got beaten by a Raspberry Pi 4 https://www.phoronix.com/review/sifive-hifive-premier-p550 https://www.phoronix.com/review/sifive-hifive-premier-p550 which the 3A6000 beats easiely https://openbenchmarking.org/vs/Processor/Loongson-3A6000,ARMv8+Cortex-A72+4-Core https://openbenchmarking.org/vs/Processor/Loongson-3A6000,AR...
    - adgjlsfhk1 2y ago
      The P550 is pretty slow. It doesn't have any SIMD, and it's scalar engine is ~about the same as a Core 2 from ~2008. In general, it's fairly confusing to me why SciFive has been so cautious in their designs. It seems like they would be in a much better place if they'd released a few CPUs where rather than trying to balance everything while creeping complexity up, they just added all the power to theoretically match high end CPUs and then addressed the bottlenecks over iterations.
      - brucehoult 2y ago
        > The P550 is pretty slow. It doesn't have any SIMD, and it's scalar engine is ~about the same as a Core 2 from ~2008. Yes! And this is great progress in just a couple of years. The previous SiFive core that made it to available hardware, the U74, is about like a Pentium or PowerPC 603 in µarch, though with higher clock speed so putting it more like late Pentium 3 or PowerPC G4 in delivered performance (and also quad core, not single core, which helps a lot). SiFive already have 2 1/2 generations of core released since the P550 in mid 2021, the P670 and the P870(-D). Both of those implement RVV (Vector). If not for US sanctions we'd be seeing very nice 16x P670 machines this year, likely quite a bit better than the Pi 5 (and Rock 5 and Orange Pi 5). Or somewhere between Sandy Bridge and Skylake in Intel terms, I think. The P870 is somewhere around Snapdragon 8 gen 2. It just takes time to get CPU cores from the drawing board to shops, and especially for a company that wants to make consumer products to license the core in the first place since SiFive (like Arm) doesn't make chips. RISC-V is behind Arm, but the gap in cores available to license is far smaller (about 2 years at present) than the gap in things anyone can buy in a shop (about 5 years at present) and getting smaller all the time. > it's fairly confusing to me why SciFive has been so cautious in their designs. It seems like they would be in a much better place if they'd released a few CPUs where rather than trying to balance everything while creeping complexity up, they just added all the power to theoretically match high end CPUs Because most of the market (by volume / revenue / profit) does not need the highest end CPUs. Even in phones the Galaxy S25, with its Qualcomm Oryon cores, is a nice headline product, but there are still new SoCs and phones being introduced today (or at least there were some in February 2024 ... I haven't checked recently) with nothing faster than Arm A53 cores announced in 2012. I expect those low end phones are still selling in pretty big numbers.

acka 2y ago

It is a sad day in history to see both a RISC-V-related acronym and NDA used in the same sentence. The term oxymoron barely cuts it IMO. I thought that RISC-V used to stand for open hardware and freedom, TIL.

boredatoms 2y ago
Riscv is an open ISA specification, not implementation Organizations are free to make closed and even secret implementations of it if they like
- ksec 2y ago
  That was not what the RISC-V supporters promised.
  - snvzz 2y ago
    Most "RISC-V supporter" do at the very least understand what RISC-V is, and what it isn't. I have never seen an actual RISC-V supporter confuse ISA and microarchitecture.
  - boredatoms 2y ago
    Who/where are those people, because they seem very misinformed
rwmj 2y ago
The RISC-V specs are all free to download and implement. Some (by no means all) implementations are proprietary. Red Hat (the company I work for) talks to all sorts of server vendors, x86, Arm, POWER, RISC-V all the time under NDA so we can find out what new products those vendors are developing before they are released, and have software ready in time. The software we write is all open sourced. This is nothing particular to do with RISC-V, and has nothing to do with the RISC-V ISA, nor with open sourcing of software.