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RISC-V RVA23 Profile: A major milestone

80 points by fork-bomber 1y ago

fidotron 1y ago
The question we all want the answer to is what is the current most likely contender for a decent performance widely available implementation of this profile, and when is it due?
- jitl 1y ago
  After Chimera Linux’s pessimistic view on RISC-V application processors, I’m not holding my breath https://chimera-linux.org/news/2025/03/dropping-riscv.html https://chimera-linux.org/news/2025/03/dropping-riscv.html Note they eventually received a donation of CPU time that allows them to continue RISC-V support but it’s still a grim situation.
  - galangalalgol 1y ago
    This release adds the cray style variable length vector instructions. Compiling with avx512 and running without it will crash, but this just uses whatever length the chip supports with the same instruction. Also means you don't have to wait on llvm to update every time they grow the vector size.
  - brucehoult 1y ago
    Yes, they got access to a $2500 RISC-V machine that's been out for a year but isn't currently available because the same manufacturer has much updated machines coming out soon. $2500 is more than a Raspberry Pi but not expensive for any organisation that is paying even one salary to one employee. I also note they recently got an Ampere Altra arm64 machine, which I believe start at around $4000. Anyway, they blogged saying they were dropping RISC-V on March 12, got access to a RISC-V machine a couple of days later, mucked around a bit with build systems (including building a new Linux kernel that didn't advertise the pre-ratification V extension, which is a checkbox in `make menuconfig`) and then on March 20 -- 8 days after the initial post -- blogged that they had successfully completed a build of their distro on the donated RISC-V machine. I don't know how long that complete build of all their packages took (Chimera Linux repo contains 11057 packages), but it can't have been more than 3 or 4 days, maybe less, which seems very reasonable. I'm not sure what is "grim" here. It's a very new ISA -- first ratified only in July 2019, and with very significant additions in November 2021 and more very important things (for RVA23, which will be the baseline for Android and also for Ubuntu 26.04 LTS) right up to 2024. Machines are only going to get faster and cheaper from this point on, but a $2500 64 core 128 GB RAM machine from January 2024 that can build a complete distro in a couple of days isn't bad at all.
- rwmj 1y ago
  I'm not aware of any chips, even in development, that will genuinely have full RVA23 support. If you'll settle for "near enough" then my betting is we'll have SiFive P650/P670 hardware first (https://www.sifive.com/cores/performance-p650-670 https://www.sifive.com/cores/performance-p650-670). There are some other development boards coming (sorry, under NDA!) that should have near-RVA23 + Xeon-like performance and we should get them in very end 2025 / early 2026. These are server-class parts so the development boards will not be cheap. Some parts of RVA23 like a complete implementation of the vector sub-extensions, and hypervisor support, are pretty complex.[1] If you just want RVA23 now (with poor performance) then qemu implements it. We found it's not very useful for software development, not just because it's slow, but also because it performs so differently from the real hardware, so you cannot, for example, optimize your vectorized code. [1] I wrote a general article about RISC-V extensions last year: https://research.redhat.com/blog/article/risc-v-extensions-whats-available-and-how-to-find-it/ https://research.redhat.com/blog/article/risc-v-extensions-w...
  - pantalaimon 1y ago
    > There are some other development boards coming (sorry, under NDA!) that should have near-RVA23 + Xeon-like performance and we should get them in 2026. These are server-class parts so the development boards will not be cheap. I can get a 3A6000 system for 400€ with decent (~Zen2) performance, are we talking more than that?
    - rwmj 1y ago
      [deleted - didn't realise you were talking about loongarch, see reply below]
      - pantalaimon 1y ago
        But RISC-V predates loongarch64 - why did Loongson create a new ISA instead of implementing a fast RISC-V core? Sure you can move faster if you can make your own standards and don't have to coordinate with anyone, but still makes me wonder if there is some fundamental issue that makes it difficult to create a high performance RISC-V implementation.
- camel-cdr 1y ago
  My bets are on Tenstorrent Ascalon. They are currently taping out and planning to release a 8 core@2.25GHz devboard and laptop next year. The cores have an 8 wide decode/issue/dispatch and dual issue 256-bit RVV support. Their the scalar part of their scheduling model is already upstream in LLVM as tt-ascalon-d8. See also: https://youtu.be/ttQtC1dQqwo https://youtu.be/ttQtC1dQqwo The only I can think of that may deliver earlier is Ventana with the Veyron V2, they plan to have chiplets in the first half of this year. I'm not sure if they are planning on releasing devboards though, as they target big servers. The cores have a 16 issue backend, with 5 512-bit RVV execution units (arithmetic,mask,permut,load,store) and a decode of up to 10 instructions per cycle. See also: https://youtu.be/OPgjCjNhqKQ https://youtu.be/OPgjCjNhqKQ Both of these claim to support full RVA23 and are high perf OoO cores.
justahuman74 1y ago
The link is pretty light on details, should this be replaced with the 'read more' link within
- rwmj 1y ago
  Maybe link straight to the profile: https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#Profiles https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/161547...
bagswatchesus 1y ago
[dead]
bjourne 1y ago
I don't get why they decided to create all these very complicated extensions before even getting solid hardware for the base instruction set. RVV support is many, many years into the future and I bet many of its instructions will be micro coded since they aren't very useful for compilers anyway. Specifying standards for the future before you have working prototypes is very (ahaha) risky.
- beej71 1y ago
  I can only speculate that the base was insufficient for high commercial traction.
- panick21_ 1y ago
  There is solid hardware, it just not standard hardware for consumers. RVV support in software is already good and there are already many commercial chips. > I bet many of its instructions will be micro coded since they aren't very useful for compilers anyway I have listened to a lot of the talks about RISC-V and many about Vector extension, and micro-coding was barley mentioned. What is more common is that people don't implement all the instructions in academic settings. > Specifying standards for the future before you have working prototypes is very (ahaha) risky. Absolutely nothing is standardized before hardware implementations exist. In fact, for Vector there was a first generation of the 0.7 that saw limited commercial use and far more more for the RVV 1.0 version.
  - bjourne 1y ago
    I looked at RISC-V SoCs last year and I couldn't find anything at all with support for RVV. Just a lot of "coming soon", "in progress", and "preorder now". Maybe the situation has improved since then.
    - brucehoult 1y ago
      When last year? The CanMV-K230 has RVV 1.0 and shipped in November 2023, just two years after RVV 1.0 was ratified. So "nothing at all" was already false before January 1 last year. The BPI-F3 (8x X60 cores with 256 bit VLEN RVV 1.0) was announced in February 2024 and shipped in May. The Lichee Pi 3A and Milk-V Jupiter with the same SoC were not far behind it, and the MuseBook and DC-Roma II laptops were not far behind them. We now also have the Orange Pi RV2 with the same SoC for $30 (2 GB RAM) to $50 (8 GB) It's probably going to be a while before we see the next generation but there are half a dozen different machines available with the current best mass-production RVV 1.0 chip.
benob 1y ago
[flagged]
deleted 1y ago
[deleted]
fithisux 1y ago
I wish there was something like RISC-V for CPU Peripherals. A standard architecture and monitoring interfaces so that more OSes could be easily booted.
- brucehoult 1y ago
  Virtio
- snvzz 1y ago
  These exist. See SBI, BRS, etc. RISC-V standards. Lots of effort actually goes into these.
  - fithisux 1y ago
    Thank you

80 points by fork-bomber 1y ago

The question we all want the answer to is what is the current most likely contender for a decent performance widely available implementation of this profile, and when is it due?

jitl 1y ago
After Chimera Linux’s pessimistic view on RISC-V application processors, I’m not holding my breath https://chimera-linux.org/news/2025/03/dropping-riscv.html https://chimera-linux.org/news/2025/03/dropping-riscv.html Note they eventually received a donation of CPU time that allows them to continue RISC-V support but it’s still a grim situation.
- galangalalgol 1y ago
  This release adds the cray style variable length vector instructions. Compiling with avx512 and running without it will crash, but this just uses whatever length the chip supports with the same instruction. Also means you don't have to wait on llvm to update every time they grow the vector size.
- brucehoult 1y ago
  Yes, they got access to a $2500 RISC-V machine that's been out for a year but isn't currently available because the same manufacturer has much updated machines coming out soon. $2500 is more than a Raspberry Pi but not expensive for any organisation that is paying even one salary to one employee. I also note they recently got an Ampere Altra arm64 machine, which I believe start at around $4000. Anyway, they blogged saying they were dropping RISC-V on March 12, got access to a RISC-V machine a couple of days later, mucked around a bit with build systems (including building a new Linux kernel that didn't advertise the pre-ratification V extension, which is a checkbox in `make menuconfig`) and then on March 20 -- 8 days after the initial post -- blogged that they had successfully completed a build of their distro on the donated RISC-V machine. I don't know how long that complete build of all their packages took (Chimera Linux repo contains 11057 packages), but it can't have been more than 3 or 4 days, maybe less, which seems very reasonable. I'm not sure what is "grim" here. It's a very new ISA -- first ratified only in July 2019, and with very significant additions in November 2021 and more very important things (for RVA23, which will be the baseline for Android and also for Ubuntu 26.04 LTS) right up to 2024. Machines are only going to get faster and cheaper from this point on, but a $2500 64 core 128 GB RAM machine from January 2024 that can build a complete distro in a couple of days isn't bad at all.
rwmj 1y ago
I'm not aware of any chips, even in development, that will genuinely have full RVA23 support. If you'll settle for "near enough" then my betting is we'll have SiFive P650/P670 hardware first (https://www.sifive.com/cores/performance-p650-670 https://www.sifive.com/cores/performance-p650-670). There are some other development boards coming (sorry, under NDA!) that should have near-RVA23 + Xeon-like performance and we should get them in very end 2025 / early 2026. These are server-class parts so the development boards will not be cheap. Some parts of RVA23 like a complete implementation of the vector sub-extensions, and hypervisor support, are pretty complex.[1] If you just want RVA23 now (with poor performance) then qemu implements it. We found it's not very useful for software development, not just because it's slow, but also because it performs so differently from the real hardware, so you cannot, for example, optimize your vectorized code. [1] I wrote a general article about RISC-V extensions last year: https://research.redhat.com/blog/article/risc-v-extensions-whats-available-and-how-to-find-it/ https://research.redhat.com/blog/article/risc-v-extensions-w...
- pantalaimon 1y ago
  > There are some other development boards coming (sorry, under NDA!) that should have near-RVA23 + Xeon-like performance and we should get them in 2026. These are server-class parts so the development boards will not be cheap. I can get a 3A6000 system for 400€ with decent (~Zen2) performance, are we talking more than that?
  - rwmj 1y ago
    [deleted - didn't realise you were talking about loongarch, see reply below]
    - pantalaimon 1y ago
      But RISC-V predates loongarch64 - why did Loongson create a new ISA instead of implementing a fast RISC-V core? Sure you can move faster if you can make your own standards and don't have to coordinate with anyone, but still makes me wonder if there is some fundamental issue that makes it difficult to create a high performance RISC-V implementation.
camel-cdr 1y ago
My bets are on Tenstorrent Ascalon. They are currently taping out and planning to release a 8 core@2.25GHz devboard and laptop next year. The cores have an 8 wide decode/issue/dispatch and dual issue 256-bit RVV support. Their the scalar part of their scheduling model is already upstream in LLVM as tt-ascalon-d8. See also: https://youtu.be/ttQtC1dQqwo https://youtu.be/ttQtC1dQqwo The only I can think of that may deliver earlier is Ventana with the Veyron V2, they plan to have chiplets in the first half of this year. I'm not sure if they are planning on releasing devboards though, as they target big servers. The cores have a 16 issue backend, with 5 512-bit RVV execution units (arithmetic,mask,permut,load,store) and a decode of up to 10 instructions per cycle. See also: https://youtu.be/OPgjCjNhqKQ https://youtu.be/OPgjCjNhqKQ Both of these claim to support full RVA23 and are high perf OoO cores.

justahuman74 1y ago

The link is pretty light on details, should this be replaced with the 'read more' link within

rwmj 1y ago
Maybe link straight to the profile: https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#Profiles https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/161547...

bagswatchesus 1y ago

[dead]

bjourne 1y ago

I don't get why they decided to create all these very complicated extensions before even getting solid hardware for the base instruction set. RVV support is many, many years into the future and I bet many of its instructions will be micro coded since they aren't very useful for compilers anyway. Specifying standards for the future before you have working prototypes is very (ahaha) risky.

beej71 1y ago
I can only speculate that the base was insufficient for high commercial traction.
panick21_ 1y ago
There is solid hardware, it just not standard hardware for consumers. RVV support in software is already good and there are already many commercial chips. > I bet many of its instructions will be micro coded since they aren't very useful for compilers anyway I have listened to a lot of the talks about RISC-V and many about Vector extension, and micro-coding was barley mentioned. What is more common is that people don't implement all the instructions in academic settings. > Specifying standards for the future before you have working prototypes is very (ahaha) risky. Absolutely nothing is standardized before hardware implementations exist. In fact, for Vector there was a first generation of the 0.7 that saw limited commercial use and far more more for the RVV 1.0 version.
- bjourne 1y ago
  I looked at RISC-V SoCs last year and I couldn't find anything at all with support for RVV. Just a lot of "coming soon", "in progress", and "preorder now". Maybe the situation has improved since then.
  - brucehoult 1y ago
    When last year? The CanMV-K230 has RVV 1.0 and shipped in November 2023, just two years after RVV 1.0 was ratified. So "nothing at all" was already false before January 1 last year. The BPI-F3 (8x X60 cores with 256 bit VLEN RVV 1.0) was announced in February 2024 and shipped in May. The Lichee Pi 3A and Milk-V Jupiter with the same SoC were not far behind it, and the MuseBook and DC-Roma II laptops were not far behind them. We now also have the Orange Pi RV2 with the same SoC for $30 (2 GB RAM) to $50 (8 GB) It's probably going to be a while before we see the next generation but there are half a dozen different machines available with the current best mass-production RVV 1.0 chip.

benob 1y ago

[flagged]

deleted 1y ago

[deleted]

fithisux 1y ago

I wish there was something like RISC-V for CPU Peripherals. A standard architecture and monitoring interfaces so that more OSes could be easily booted.

brucehoult 1y ago
Virtio
snvzz 1y ago
These exist. See SBI, BRS, etc. RISC-V standards. Lots of effort actually goes into these.
- fithisux 1y ago
  Thank you