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If you're taking priority requests: "How coding FPGA differs from GPU and what is High-Level Synthesis, Verilog, and VHDL? #36" Yes please!
by EliRivers 1y ago
If you're taking priority requests:
"How coding FPGA differs from GPU and what is High-Level Synthesis, Verilog, and VHDL? #36" Yes please!
- ashvardanian 1y agoI've started implementing this, but organizing a good testing environment was time-consuming. If someone here has a sandbox and the right skill set, 3x3x3 or 4x4x4 matrix multiplications can be a perfect candidate for FPGA ports and case studies!
- synthos 1y agoWhat data type/precision? How much parallelism versus iterative? Is this fully in fabric or part of a SoC? Easy to get mired in many details. HW design has so many degrees of freedom which makes it fun but challenging. What specific topics are you trying to address with this?
- ashvardanian 1y agoShowing the tradeoffs between complexity & throughput of HLS and HDL implementations is the goal. I assume, uint8 should be sufficient to make a point?
- almostgotcaught 1y agoThere is no "coding FPGA". Verilog/VHDL are not programming languages, they are "hardware description languages" (HDL). That means when you write those languages literally what you're doing is specifying every single wire in the circuit. People that do FPGA work aren't even called programmers, they're called designers. > High-Level Synthesis Something that absolutely not a single professional designer uses.
- ashvardanian 1y agoI agree that the sentiment around HLS is very bad, but there aren’t many good examples online, showcasing the difference. Do you think HDL vs HLS tradeoffs will be visible on something like 8-bit unsigned integer 3x3x3 or 4x4x4 matrix-multiplication?