4 ms·
Super cool. Imagine specialized hardware for running these.
by justanotheratom 1y ago
Super cool. Imagine specialized hardware for running these.
- LargoLasskhyfv 1y agoIt already exists. Dynamically reconfigurable. Some smartass designed it alone on ridiculously EOL'd FPGAs. Meanwhile ASICs in small batches without FPGA baggage were produced. Unfortunately said smartass is under heavy NDA. Or luckily, because said NDA paid very well for him.
- djmips 1y agoNicely done!
- LargoLasskhyfv 1y agoWas actually sort of a sideways pivot, and hard for me to do, because of the involved mathematics. Initially it was more of general 'architecture astronautics' in the context of dynamically reconfigurability/systolic arrays/transport triggered architecture/VLIW, which got me some nice results. Having read and thought much about balanced ternary hardware, and 'playing' with that, while also reading how this could be favourably applicable to ML lead to that 'pivot'. A few years before 'this', I might add. Now I can 'play' much more relaxed and carefree, to see what else I can get out of this :-)
- llama_drama 1y agoI wonder if instructions like VPTERNLOGQ would help speed these up