I hope that as RISC-V gains in support, there is a chance to experiment with a many-core version of it. Something like a hundred QERV cores on a chip. The lack

I hope that as RISC-V gains in support, there is a chance to experiment with a many-core version of it. Something like a hundred QERV cores on a chip. The lack of patents is a key enabler, and support for the ISA on more vanilla chips is the other enabler. This could happen. https://github.com/olofk/qerv https://github.com/olofk/qerv The only pratical many-core I know of was the SPARC T-1000 series https://en.wikipedia.org/wiki/SPARC_T_series https://en.wikipedia.org/wiki/SPARC_T_series