3 ms·
platform/x86/amd: pmc: Require at least 2.5 seconds between HW sleep cycles
- davikr 2y ago> For some situations this can be problematic because it can cause leakage from VDDCR_SOC to VDD_MISC and force VDD_MISC outside of the electrical design guide specifications. On some designs this will trip the over voltage protection feature (OVP) of the voltage regulator module, but it could cause APU damage as well.