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It is needed for the Telum chips because they have so much L2 cache per core (36MB) there isn't room for any L3 cache
by UltraSane 2y ago
It is needed for the Telum chips because they have so much L2 cache per core (36MB) there isn't room for any L3 cache
- rbanffy 2y agoThey could reduce core count to make space for on-chip L3, and add a massive amount of cache to the drawer controller, like the was on the z15, but this is way more efficient. They also keep the in-drawer and cross-socket latencies very low, forming a virtual L4 with all chips in the drawer. In the end, it's a more efficient way to allocate silicon.
- UltraSane 2y agoWould this architecture work on x86 or ARM CPUs? I'm surprised they didn't use HBM3 for CPU cache.