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> IBM’s solution is to reduce data duplication within its caches, and re-use the chip’s massive L2 capacity to create a virtual L3 cache. I was kind of fascina
by theandrewbailey 2y ago
> IBM’s solution is to reduce data duplication within its caches, and re-use the chip’s massive L2 capacity to create a virtual L3 cache.
I was kind of fascinated with the original Telum CPUs because of this feature. Do we know if other CPU designers are planning a similar virtual cache feature? Or is this feature implemented as a workaround due to some other deficiency that others don't have?
- UltraSane 2y agoIt is needed for the Telum chips because they have so much L2 cache per core (36MB) there isn't room for any L3 cache
- rbanffy 2y agoThey could reduce core count to make space for on-chip L3, and add a massive amount of cache to the drawer controller, like the was on the z15, but this is way more efficient. They also keep the in-drawer and cross-socket latencies very low, forming a virtual L4 with all chips in the drawer. In the end, it's a more efficient way to allocate silicon.
- UltraSane 2y agoWould this architecture work on x86 or ARM CPUs? I'm surprised they didn't use HBM3 for CPU cache.