Actually, I'm wrong. AMD's deep dive [1] says register use is low during BVH traversal, so they are still using shared memory for the stack. According to the I

Actually, I'm wrong. AMD's deep dive [1] says register use is low during BVH traversal, so they are still using shared memory for the stack. According to the ISA doc [2] they have a special mode for the stack that overwrites older entries instead of overflowing and a fallback stackless mode. So the register allocation is actually increased when invoking the hit shader, allowing each hit shader to use a different number of VGPRs, spinning is probably the most logical approach. They probably don't even need the deadlock avoidance mode with their current implementation, which seems to allocate the full set of registers when calling the hit shader and only free them at the end. [1] https://www.techpowerup.com/review/amd-radeon-rx-9070-series-technical-deep-dive/3.html https://www.techpowerup.com/review/amd-radeon-rx-9070-series... [2] See 12.5.3. DS Stack Operations for Ray Tracing - https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna4-instruction-set-architecture.pdf https://www.amd.com/content/dam/amd/en/documents/radeon-tech...