3 ms·
Fascinating!
by IAmLiterallyAB 2y ago
Fascinating!
- dmitrygr 2y agoThe main hang-up is that ARM uses PC as a general register a lot and in ways that make translating ARM instrs rather messy. ADD R0, SP, PC, ROR SP is entirely valid, even if nonsensical, instruction. But you must translate all valid inputs, else you risk breaking things. That may be a contrived example, but here is a common one: if one has a jumptable of relative offsets somewhere, pointed to by R10, even this is valid: LDR R0, [R10, R0, LSL #2] ADD PC, R10, R0 That gets messy to translate
- kragen 2y agoInteresting, I hadn't thought about this. Is the issue that the JIT output is likely to be a different number of bytes away? tbb/tbh seems like a more common version of that problem, TBH. As I understand it, this kind of thing was a big problem for ARM in the mid-90s when they finally wrote the ARM ARM and outlawed things like ldmia r2!, {r0-r4}.
- dmitrygr 2y agoDifferent number of bytes out than in is not an issue. Efficiently translating such constructs in the general case is hard. Imagine what it would look like.