I'm working on revitalizing a FPGA DSP from my first failed startup. It's a RISC-V processor with a vector machine glued onto the side. It's capable of 30 secon

I'm working on revitalizing a FPGA DSP from my first failed startup. It's a RISC-V processor with a vector machine glued onto the side. It's capable of 30 second rapid testing of new algorithms which normally takes hours in FPGA land. Looking for a clear way to describe this novel approach to DSP.