3 ms·

I wonder if you could bit-bang PS2 from the host side - though this is probably one of those things where we need to "consider if we should."

kragen 2y ago
Yes, the PS/2 keyboard protocol is the AT keyboard protocol, which is pretty easy to bitbang on processors that aren't extremely slow.
mjevans 2y ago
https://en.wikipedia.org/wiki/PS/2_port#Conversion_between_PS/2_and_USB https://en.wikipedia.org/wiki/PS/2_port#Conversion_between_P... PS/2 is a flavor of line serial communication (0 and 5V): ground, power, clock, data. "PS/2 mice send interrupts at a default rate of 100 Hz when they have data to send to the computer." Which is how a 'dual mode controller' would drive it's IO pins in a way that work for USB or PS/2. USB uses https://en.wikipedia.org/wiki/Differential_signalling https://en.wikipedia.org/wiki/Differential_signalling , which Wikipedia's article explains have the advantages of greater signal to noise ratio and resistance to some common types of data-channel noise. I don't happen to know what the _data_ voltage level of a USB link is offhand and skimming the article was insufficiently clear (Either of -5V and +5V, OR float is ~2.5V and one pulls up to Vcc the other down to Gnd make some sense.). The initial power pin level is also supposed to be ~5V. -- Also, if you mean from a typical PC... A modern AMD system's block diagram shows most USB ports driven from CPU socket pins or from the primary board chipset directly (E.G. AMD's X870E or whatever). I would be almost amazed if those weren't in house / licensed ASIC blocks with ROM firmware.
- 15155 2y ago
  > USB link is offhand 3.3V <-> GND
  - mjevans 2y ago
    The data? I checked and Ground and Power pins are 0 and 5V respectively as I recalled. This StackExchange thread has some good diagrams and useful answers: https://electronics.stackexchange.com/questions/190592/why-does-usb-have-vcc-5v-and-high-3-3v https://electronics.stackexchange.com/questions/190592/why-d... Lower speed links are suppsoed to pull the - data pin slightly negative and, effectively, a safely 'TTL high' (relative to 5V source) of greater than 2.8V. The power difference is 5V to better guard against too much loss over a long cable. Higher speed links are quoted as using even lower voltages (the graph appears 0 and 0.4 v swapped as flipped).

kragen 2y ago

Yes, the PS/2 keyboard protocol is the AT keyboard protocol, which is pretty easy to bitbang on processors that aren't extremely slow.

mjevans 2y ago

https://en.wikipedia.org/wiki/PS/2_port#Conversion_between_PS/2_and_USB https://en.wikipedia.org/wiki/PS/2_port#Conversion_between_P... PS/2 is a flavor of line serial communication (0 and 5V): ground, power, clock, data. "PS/2 mice send interrupts at a default rate of 100 Hz when they have data to send to the computer." Which is how a 'dual mode controller' would drive it's IO pins in a way that work for USB or PS/2. USB uses https://en.wikipedia.org/wiki/Differential_signalling https://en.wikipedia.org/wiki/Differential_signalling , which Wikipedia's article explains have the advantages of greater signal to noise ratio and resistance to some common types of data-channel noise. I don't happen to know what the _data_ voltage level of a USB link is offhand and skimming the article was insufficiently clear (Either of -5V and +5V, OR float is ~2.5V and one pulls up to Vcc the other down to Gnd make some sense.). The initial power pin level is also supposed to be ~5V. -- Also, if you mean from a typical PC... A modern AMD system's block diagram shows most USB ports driven from CPU socket pins or from the primary board chipset directly (E.G. AMD's X870E or whatever). I would be almost amazed if those weren't in house / licensed ASIC blocks with ROM firmware.

15155 2y ago
> USB link is offhand 3.3V <-> GND
- mjevans 2y ago
  The data? I checked and Ground and Power pins are 0 and 5V respectively as I recalled. This StackExchange thread has some good diagrams and useful answers: https://electronics.stackexchange.com/questions/190592/why-does-usb-have-vcc-5v-and-high-3-3v https://electronics.stackexchange.com/questions/190592/why-d... Lower speed links are suppsoed to pull the - data pin slightly negative and, effectively, a safely 'TTL high' (relative to 5V source) of greater than 2.8V. The power difference is 5V to better guard against too much loss over a long cable. Higher speed links are quoted as using even lower voltages (the graph appears 0 and 0.4 v swapped as flipped).