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Looks like they're claiming everything under the sun for 3). https://github.com/siliconcompiler/logiklib/blob/main/logiklib/zeroasic/z1000/README.md https://git
by Neywiny 2y ago
Looks like they're claiming everything under the sun for 3). https://github.com/siliconcompiler/logiklib/blob/main/logiklib/zeroasic/z1000/README.md https://github.com/siliconcompiler/logiklib/blob/main/logikl... and https://www.zeroasic.com/fpga-architect https://www.zeroasic.com/fpga-architect say more. I'm very skeptical though. They claim binary compatibility? I don't know what that means for an FPGA. They seem to be testing all CLB vs some DSP/BRAM macros. What does it mean to have binary compatibility between those? Usually you don't want that. The design should be optimized for the device it's on. I don't want to take an fmax hit because someone may be using a soft multiply or something like that. Only time will tell.
- addaon 2y agoEh, it’s a 4-LUT. If 4-LUTs were good enough, I’d stick with Microsemi. As it is, their only advantage over 6-LUTs is that they’re much less awkward to be overhead discussing by someone who doesn’t know FPGAs. (“6-LUTs are great” can raise some eyebrows.) The ratio of routing to compute just doesn’t match the problems I have experience with, and the reaction to rebalance this tends to be to omit other features (second outputs, shift register mode, wider muxes) that really, really pay off.
- adapteva 2y agoThe only novelty claimed here is transparency. Binary compatibility is possible by documenting the complete architecture and the sequence of bit stream loading. It only refers to devices in the same architecture (eg z1000). We'll see whether binary compatibility is a big deal to folks. Some would argue that you can always recompile the source code. There are applications where that is not an option...