3 ms·
In fact in some archs it might be even faster to make bool word-sized (i.e 8 bytes on 64 bit) if unaligned loads and stores are slower or disallowed.
by sph 2y ago
In fact in some archs it might be even faster to make bool word-sized (i.e 8 bytes on 64 bit) if unaligned loads and stores are slower or disallowed.
- Veliladon 2y agoIt'd have to be a really old one. Almost every CPU with an L1 cache loads in cache lines and loads don't have to be cache line aligned because it's supposed to be transparent to the programmer. So there's little to no penalty on modern architectures for non-aligned words. I know there hasn't been one on ARM or Intel for at least a decade. If you try to load and use consecutive words in a hot loop that are, say, 72 bytes apart you'll see a huge performance drop but that's more because you're only using 1/8th of the cache line and not because they're unaligned.