Source for the RISC-V cores being essentially free (Luke Wren is the creator of the RISC-V core design used): > The final die size would likely have been exact

Source for the RISC-V cores being essentially free (Luke Wren is the creator of the RISC-V core design used): > The final die size would likely have been exactly the same with the Hazard3 removed, as std cell logic is compressible, and there is some rounding on the die dimensions due to constraints on the pad ring design. https://nitter.space/wren6991/status/1821582405188350417 https://nitter.space/wren6991/status/1821582405188350417