It feels like just yesterday that Chips and Cheese started publishing (*checked and they started up in 2020 -- so not that long ago after all!), and now they've

It feels like just yesterday that Chips and Cheese started publishing (*checked and they started up in 2020 -- so not that long ago after all!), and now they've really become a mainstay in my silicon newsletter stack, up there with Semianalysis/Semiengineering/etc. > Intel uses a software-managed scoreboard to handle dependencies for long latency instructions. Interesting! I've seen this in compute accelerators before, but both AMD and Nvidia manage their long-latency dependency tracking in hardware so it's interesting to see a major GPU vendor taking this approach. Looking more into it, it looks like the interface their `send`/`sendc` instruction exposes is basically the same interface that the PE would use to talk to the NOC: rather than having some high-level e.g. load instruction that hardware then translates to "send a read-request to the dcache, and when it comes back increment this scoreboard slot", the ISA lets/makes the compiler state that all directly. Good for fine control of the hardware, bad if the compiler isn't able to make inferences that the hardware would (e.g. based on runtime data), but then good again if you really want to minimize area and so wouldn't have that fancy logic in the pipeline anyways.