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Opensouce RISC-V CPU core implemented in Verilog from scratch in one night
- Rochus 2y ago> implemented in Verilog from scratch in one night Cool, but the "night" actually started in 2018 and lasted over seven years and 384 commits so far ;-)
- snvzz 2y agoIt was working after just one night of work, is what they probably meant. Then they didn't discard it, but maintained it instead.
- brucehoult 2y agoSee the original 2018 post https://news.ycombinator.com/item?id=17852876 https://news.ycombinator.com/item?id=17852876
- brucehoult 2y agoSee the original 2018 post https://news.ycombinator.com/item?id=17852876 https://news.ycombinator.com/item?id=17852876