Here are some relevant slides from hpcasia25: https://github.com/RISCVtestbed/riscvtestbed.github.io/blob/main/assets/files/hpcasia25/Openchip.pdf https://githu

Here are some relevant slides from hpcasia25: https://github.com/RISCVtestbed/riscvtestbed.github.io/blob/main/assets/files/hpcasia25/Openchip.pdf https://github.com/RISCVtestbed/riscvtestbed.github.io/blob/... I also found this report on their FPGA Emulation Platform: https://www.riser-project.eu/wp-content/uploads/2024/11/RISER_D3.1_FPGA_Emulation_Platform_v1.0_Final.pdf https://www.riser-project.eu/wp-content/uploads/2024/11/RISE... So from these resources it seems like they develop a vector processor with Semidynamics out-of-order Atrevido core as a scalar core and their Vitruvius VPU. There is a paper about a previous iteration of the VPU: https://dl.acm.org/doi/10.1145/3575861 https://dl.acm.org/doi/10.1145/3575861 In the more recent report they have a vector length of 16,384 bits, with 16 lanes (8 in FPGA, 16 in the diagram, final version could be more), so total of 16*64=1024 bits of ALUs. Slide 15 seems to indicate that they want to create a chip with 32 of those cores, a shared L3 cache, and access to HBM.