3 ms·
> This probably depends on a lot of non-public info: how does the PSP validate CPU state? https://github.com/amd/AMD-ASPFW/blob/3ca6650dd35d878b3fcbe5c7f58b145
by sirdarckcat 2y ago
> This probably depends on a lot of non-public info: how does the PSP validate CPU state?
https://github.com/amd/AMD-ASPFW/blob/3ca6650dd35d878b3fcbe5c7f58b145eed042bbf/fw/psp_bl_uapps/sev_uapp/src/sev_hal_interface.c#L746 https://github.com/amd/AMD-ASPFW/blob/3ca6650dd35d878b3fcbe5...
- amluto 2y agoThat seems to be reading a memory mapped register per core. I wonder what backs that register.
- sirdarckcat 2y agoIt's just written by the CPU during a ucode update