4 ms·

Author here if anyone has questions...

• java-man 2y ago
  Ken, maybe it's time to publish a book?
  • kens 2y ago
    That would require me to focus on one subject :-)
    • JohnKemeny 2y ago
      Then publish many books?
      • ForOldHack 2y ago
        I ancient times, it would be nice to curl up to a nice scroll ,later on a nice bound book, now we are selecting the background colors on our e-readers. These articles are hard-core good. I would like to hear much more about the R4200i than the 286.
    • java-man 2y ago
      Here is an example: a certain blogger, Dave Addey [0] published a book [1] which is basically a hardcopy of the blog. After the EMP flash of 2075, the centient raccoons will enjoy reading the stories of the civilization long gone. [0] https://typesetinthefuture.com/author/typesetinthefuture/ https://typesetinthefuture.com/author/typesetinthefuture/ [1] https://www.amazon.com/Typeset-Future-Typography-Science-Fiction/dp/1419727141 https://www.amazon.com/Typeset-Future-Typography-Science-Fic...
      • fargle 2y ago
        *sentient raccoons (we are pedantic)
  • ForOldHack 2y ago
    I have to respect his choice to focus on the 8086 and the pentium, I would think he considers the 80286 a brain dead footnote, interesting as to what when wrong and what went terribly wrong. I used to teach binary math to kids, and at a county fair I was upstaged by an 11 year old girl who demonstrated both multiplication by powers of two and division of powers of two. "What does your father do for a living?' "He is the director of the laser fusion project!" "Oh."
    • kristianp 2y ago
      The 286 could process twice as many instructions per clock as an 8086. According to Wikipedia, an uplift similar to the 80486 and the Pentium over their predecessors.
      • ForOldHack 2y ago
        So that is wikipedias "opinion" which any one could edit. I should edit that to reflect where the performance came from. Always check sources. ( The reference comes from intel386. com)
        • ForOldHack 2y ago
          The cited website went offline this morning, and it does not discuss the execution rate of the 286, NOR does it discuss the reserved bytes in the GDT, and LDTs. Not a lot of confirmation.... https://web.archive.org/web/20160204052256/http://intel80386.com/386htm/s13_02.htm https://web.archive.org/web/20160204052256/http://intel80386... " For those descriptors that are common to both the 80286 and the 80386, the presence of zeros in the final word causes the 80386 to interpret these descriptors exactly as 80286 does; for example: " This is patently and documented as untrue. The final word is reserved for use as a 365 GDT, and breaks 286 code, specifically Xenix 286, on a 386. https://www.os2museum.com/wp/theres-more-to-the-286-xenix-story/ https://www.os2museum.com/wp/theres-more-to-the-286-xenix-st...
• dsvf 2y ago
  No question, but just in general appreciation for the wonderful content you put out there that we get to enjoy!
• vanderZwan 2y ago
  What happened to the dedicated "times three" multiplier in later machines? Did some form of it stick around? Did they change tactics to something making it obsolete?
  • kens 2y ago
    There were a lot of different algorithms in use back then. I don't know if there is a winner used in modern chips.
  • phire 2y ago
    Obsolete. You can observe the evolution of multipliers in the MIPS line, which I've been studying, and happen to know. The R3000A had the same Radix-8 (aka 3-bit per cycle) integer multiplier in 1989. The R4000 had two Radix-8 multipliers in 1991. One for integer, one for floating point. The R4400 was an upgraded R4000 in 1992. The integer multiplier was kept at Radix-8, but the FPU was upgraded to a Radix-256 design (aka 8-bits per cycle). In parallel, MIPS spent a lot of time creating a low power design for the target market of "Windows NT laptops". The result was the R4200, released in 1993. MIPS published quite a bit of information about the various power saving optimisations [1], [2]. Instead of seperate integer and floating point data paths, they created a unified data path that did both, allowing them to use the same Radix-8 multiplier for everything. They even unified the multiplier unit into the main adder, rather than using a seperate adder like earlier designs. In 1995, MIPS released the R4300i, (aka the CPU found in the Nintendo 64). It was an evolution of the r4200, keeping the unified float/integer datapath. But it gained the Radix-256 multiplier from the R4400 design, so both integer and float instructions complete at 8-bits per cycle. As far as I can tell, this Radix-256 multiplier doesn't use any fancy tricks. It's just an array of eight 64-bit wide carry-save adders, feeding into a regular carry-lookahead adder. In 1996, MIPS released the R10000. Transistors are now cheap enough that they could implement a full 52-bit adder for their floating point data path, allowing them to issue one double precision multiplication every cycle (though it's pipelined with a 2 cycle latency). I assumes it's just 52 stacked adders, though seems like they probably need to be doing something fancier with carries by the time it's that big. Most modern CPUs have ended up at the same point. Massive pipelined arrays of adders that can execute one 64-bit multiplication every cycle, with a 3 cycle latency. [1] https://www.youtube.com/watch?v=nll5MWlG7q4 https://www.youtube.com/watch?v=nll5MWlG7q4 [2] https://ieeexplore.ieee.org/document/282948/ https://ieeexplore.ieee.org/document/282948/
• dwedge 2y ago
  I only tenuously understand this so feel free to ignore the question if it's too asinine but: > (What about ×5? If you can compute ×3, you can subtract that from ×8 to get ×5.) Why can't you do the same to subtract x4 from x7 to get x3?
  • mikequinlan 2y ago
    x7 is computed by x8 - x, so you get x8 - x - x4 which is 2 subtractions (and 2 delays). You only want 1 delay.
  • thombat 2y ago
    Because x8 is simply shifting 3 bits left so it's "free" (fixed-sized shifts are very simple to implement), whereas generating the x7 would require the additional circuitry, which additionally will be more expensive than the x3 was (since it's another shift+add beyond what x3 required)
  • russdill 2y ago
    The question would be why isn't it 4x - 1x?
    • kens 2y ago
      The trick is that Booth's algorithm gives you the ×8 term for free; you multiply by one more in the next base-8 digit. You can put either ×4 or -×1 into a term, but you can't put both of them into one term. So you can do ×8 - ×1 but you can't do ×4 - ×1.
      • eru 2y ago
        I guess the decimal equivalent would be multiplying by 10 vs multiplying by 5. Or for hexadecimal: multiplying by 0x10 (16) or by 2, 4 or 8.
    • mjevans 2y ago
      I suspect it's logically equivalent, but one bit wider in hardware. Binary 4x is left shift by 2, rather than 2x which is by one. Adding or subtracting in 2's compliment space is the same operation for the bits of the word.
• kristianp 2y ago
  This is probably a basic question, but is this for floating point multiplies? Isn't the part thats being multiplied less than 64 bits because you also add the exponents?
  • kens 2y ago
    Yes, this is for floating point multiplies. But internally, the FPU uses x86 extended-precision numbers, 80-bit floats, with 64 bits of significand and 15 exponent bits. So the multiplier is dealing with 64-bit numbers, plus a few more bits to support rounding correctly. https://en.wikipedia.org/wiki/Extended_precision#x86_extended-precision_format https://en.wikipedia.org/wiki/Extended_precision#x86_extende...
• rob74 2y ago
  Not really a question, just one phrase that left me scratching my head a bit: > The downside to radix-8 multiplication is that multiplying by a number from 0 to 7 is much more complicated than multiplying by 0 or 1, which is almost trivial. I think you can leave out the "almost" there - multiplying by 0 is 0 and multiplying by 1 is the number itself, as shown in the example, so I would definitely call it trivial.