AMD also has a long history of using half-width, double-pumped SIMD implementations. It worked each time. With Zen 4 the surprise wasn't that it worked at all,

AMD also has a long history of using half-width, double-pumped SIMD implementations. It worked each time. With Zen 4 the surprise wasn't that it worked at all, but how well it worked and how little the core grew in any relevant metric to support it: size, static and dynamic power. It makes me wonder why Intel didn't pair two efficiency cores with half width SIMD data paths per core sharing a single full width permute unit between them.