5 ms·

I find it irritating that they are comparing clock scaling to the venerable Skylake-X. Surely Sapphire Rapids has been out for almost 2 years by now.

fuhsnn 2y ago
I think it's mostly the lack of comparable research other than the Skylake-X one by Travis Downs. I too would like to see how Zen 4 behaves in the situation with its double-pumping.
eqvinox 2y ago
Seemed appropriate to me as comparing the "first core to use full-width AVX-512 datapaths"; my interpretation is that AMD threw more R&D into this than Intel before shipping it to customers… (It's also not really a comparative article at all? Skylake-X is mostly just introduction…)
- kristianp 2y ago
  > my interpretation is that AMD threw more R&D into this than Intel before shipping it to customers AMD had the benefit of learning from Intel's mistakes in their first generation of AVX-512 chips. It seemed unfair to compare an Intel chip that's so old (albeit long-lasting due to Intel's scaling problems). Skylake-X chips were released in 2017! [1] [1] https://en.wikipedia.org/wiki/Skylake_(microarchitecture)#High-end_desktop_processors_(Skylake-X) https://en.wikipedia.org/wiki/Skylake_(microarchitecture)#Hi...
  - eqvinox 2y ago
    sure, but AMD's decision to start with a narrower datapath happened without insight from Intel's mistakes and could very well have backfired (if Intel had managed to produce a better-working implementation faster, that could've cost AMD a lot of market share). Intel had the benefit of designing the instructions along with the implementation as well, and also the choice of starting on a 2x256 datapath... And again, yeah it's not great were it a comparison, but it really just doesn't read as a comparison to me at all. It's a reference.
    - adrian_b 2y ago
      AMD did not start with a narrower datapath, even if this is a widespread myth. It only had a narrower path between the inner CPU core and the L1 data cache memory. The most recent Intel and AMD CPU cores (Lion Cove and Zen 5) have identical vector datapath widths, but for many years, for 256-bit AVX Intel had a narrower datapath than AMD, 768-bit for Intel (3 x 256-bit) vs. 1024-bit for AMD (4 x 256-bit). Only when executing 512-bit AVX-512 instructions, the vector datapath of Intel was extended to 1024-bit (2 x 512-bit), matching the datapath used by AMD for any vector instructions. There were only 2 advantages of Intel AVX-512 vs. AMD executing AVX or the initial AVX-512 implementation of Zen 4. The first was that some Intel CPU models, but only the more expensive SKUs, i.e. most of the Gold and all of the Platinum, had 2 x 512-bit FMA units, while the cheap Intel CPUs and AMD Zen 4 had only one 512-bit FMA unit (but AMD Zen 4 still had 2 x 512-bit FADD units). Therefore Intel could do 2 FMUL or FMA per clock cycle, while Zen 4 could do only 1 FMUL or FMA (+ 1 FADD). The second was that Intel had a double width link to the L1 cache, so it could do 2 x 512-bit loads + 1 x 512-bit stores per clock cycle, while Zen 4 could do only 1 x 512-bit loads per cycle + 1 x 512-bit stores every other cycle. (In a balanced CPU core design the throughput for vector FMA and for vector loads from the L1 cache must be the same, which is true for both old and new Intel and AMD CPU cores.) With the exception of vector load/store and FMUL/FMA, Zen 4 had the same or better AVX-512 throughput for most instructions, in comparison with Intel Sapphire Rapids/Emerald Rapids. There were a few instructions with a poor implementation on Zen 4 and a few instructions with a poor implementation on Intel, where either Intel or AMD were significantly better than the other.
      - eqvinox 2y ago
        > AMD did not start with a narrower datapath, even if this is a widespread myth. It only had a narrower path between the inner CPU core and the L1 data cache memory. https://www.mersenneforum.org/node/21615#post614191 https://www.mersenneforum.org/node/21615#post614191 "Thus as many of us predicted, 512-bit instructions are split into 2 x 256-bit of the same instruction. And 512-bit is always half-throughput of their 256-bit versions." Is that wrong? There's a lot of it being described as "double pumped" going around… (tbh I couldn't care less about how wide the interface buses are, as long as they can deliver in sum total a reasonable bandwidth at a reasonable latency… especially on the further out cache hierarchies the latency overshadows the width so much it doesn't matter if it comes down to 1×512 or 2×256. The question at hand here is the total width of the ALUs and effective IPC.)
adrian_b 2y ago
True, but who would bother to pay a lot of money for a CPU that is known to be inferior to alternatives, only to be able to test the details of its performance.
- crest 2y ago
  A well funded investigative tech journalist?
  - adrian_b 2y ago
    With prices in the range $2,000 - $20,000 for the CPU, plus a couple grand for at least MB, cooler, memory and PSU, the journalist must be very well funded to spend that much for publishing one article analyzing the CPU. I would like to read such an article or to be able to test myself such a CPU, but my curiosity is not so great as to make me spend such money. For now, the best one can do is to examine the results of general-purpose benchmarks published on sites like: https://www.servethehome.com/ https://www.servethehome.com/ https://www.phoronix.com/ https://www.phoronix.com/ where Intel, AMD or Ampere send some review systems with Xeon, Epyc or Arm-based server CPUs. These sites are useful, but a more thorough micro-architectural investigation would have been nice.
- kristianp 2y ago
  AWS, dedicated EC2 instance. A few dollars an hour.
formerly_proven 2y ago
Cascade Lake improved the situation a bit, but then you had Ice Lake where iirc the hard cutoffs were gone and you were just looking at regular power and thermal steering. IIRC, that was the first generation where we enabled AVX512 for all workloads.
Earw0rm 2y ago
Depending on which CPU category. I think Intel HEDT stops at Cascade Lake, which is essentially Skylake-X Refresh from 2019? Whereas AMD has full-fat AVX512 even in gaming laptop CPUs.
deleted 2y ago
[deleted]

fuhsnn 2y ago

I think it's mostly the lack of comparable research other than the Skylake-X one by Travis Downs. I too would like to see how Zen 4 behaves in the situation with its double-pumping.

eqvinox 2y ago

Seemed appropriate to me as comparing the "first core to use full-width AVX-512 datapaths"; my interpretation is that AMD threw more R&D into this than Intel before shipping it to customers… (It's also not really a comparative article at all? Skylake-X is mostly just introduction…)

kristianp 2y ago
> my interpretation is that AMD threw more R&D into this than Intel before shipping it to customers AMD had the benefit of learning from Intel's mistakes in their first generation of AVX-512 chips. It seemed unfair to compare an Intel chip that's so old (albeit long-lasting due to Intel's scaling problems). Skylake-X chips were released in 2017! [1] [1] https://en.wikipedia.org/wiki/Skylake_(microarchitecture)#High-end_desktop_processors_(Skylake-X) https://en.wikipedia.org/wiki/Skylake_(microarchitecture)#Hi...
- eqvinox 2y ago
  sure, but AMD's decision to start with a narrower datapath happened without insight from Intel's mistakes and could very well have backfired (if Intel had managed to produce a better-working implementation faster, that could've cost AMD a lot of market share). Intel had the benefit of designing the instructions along with the implementation as well, and also the choice of starting on a 2x256 datapath... And again, yeah it's not great were it a comparison, but it really just doesn't read as a comparison to me at all. It's a reference.
  - adrian_b 2y ago
    AMD did not start with a narrower datapath, even if this is a widespread myth. It only had a narrower path between the inner CPU core and the L1 data cache memory. The most recent Intel and AMD CPU cores (Lion Cove and Zen 5) have identical vector datapath widths, but for many years, for 256-bit AVX Intel had a narrower datapath than AMD, 768-bit for Intel (3 x 256-bit) vs. 1024-bit for AMD (4 x 256-bit). Only when executing 512-bit AVX-512 instructions, the vector datapath of Intel was extended to 1024-bit (2 x 512-bit), matching the datapath used by AMD for any vector instructions. There were only 2 advantages of Intel AVX-512 vs. AMD executing AVX or the initial AVX-512 implementation of Zen 4. The first was that some Intel CPU models, but only the more expensive SKUs, i.e. most of the Gold and all of the Platinum, had 2 x 512-bit FMA units, while the cheap Intel CPUs and AMD Zen 4 had only one 512-bit FMA unit (but AMD Zen 4 still had 2 x 512-bit FADD units). Therefore Intel could do 2 FMUL or FMA per clock cycle, while Zen 4 could do only 1 FMUL or FMA (+ 1 FADD). The second was that Intel had a double width link to the L1 cache, so it could do 2 x 512-bit loads + 1 x 512-bit stores per clock cycle, while Zen 4 could do only 1 x 512-bit loads per cycle + 1 x 512-bit stores every other cycle. (In a balanced CPU core design the throughput for vector FMA and for vector loads from the L1 cache must be the same, which is true for both old and new Intel and AMD CPU cores.) With the exception of vector load/store and FMUL/FMA, Zen 4 had the same or better AVX-512 throughput for most instructions, in comparison with Intel Sapphire Rapids/Emerald Rapids. There were a few instructions with a poor implementation on Zen 4 and a few instructions with a poor implementation on Intel, where either Intel or AMD were significantly better than the other.
    - eqvinox 2y ago
      > AMD did not start with a narrower datapath, even if this is a widespread myth. It only had a narrower path between the inner CPU core and the L1 data cache memory. https://www.mersenneforum.org/node/21615#post614191 https://www.mersenneforum.org/node/21615#post614191 "Thus as many of us predicted, 512-bit instructions are split into 2 x 256-bit of the same instruction. And 512-bit is always half-throughput of their 256-bit versions." Is that wrong? There's a lot of it being described as "double pumped" going around… (tbh I couldn't care less about how wide the interface buses are, as long as they can deliver in sum total a reasonable bandwidth at a reasonable latency… especially on the further out cache hierarchies the latency overshadows the width so much it doesn't matter if it comes down to 1×512 or 2×256. The question at hand here is the total width of the ALUs and effective IPC.)

adrian_b 2y ago

True, but who would bother to pay a lot of money for a CPU that is known to be inferior to alternatives, only to be able to test the details of its performance.

crest 2y ago
A well funded investigative tech journalist?
- adrian_b 2y ago
  With prices in the range $2,000 - $20,000 for the CPU, plus a couple grand for at least MB, cooler, memory and PSU, the journalist must be very well funded to spend that much for publishing one article analyzing the CPU. I would like to read such an article or to be able to test myself such a CPU, but my curiosity is not so great as to make me spend such money. For now, the best one can do is to examine the results of general-purpose benchmarks published on sites like: https://www.servethehome.com/ https://www.servethehome.com/ https://www.phoronix.com/ https://www.phoronix.com/ where Intel, AMD or Ampere send some review systems with Xeon, Epyc or Arm-based server CPUs. These sites are useful, but a more thorough micro-architectural investigation would have been nice.
kristianp 2y ago
AWS, dedicated EC2 instance. A few dollars an hour.

formerly_proven 2y ago

Cascade Lake improved the situation a bit, but then you had Ice Lake where iirc the hard cutoffs were gone and you were just looking at regular power and thermal steering. IIRC, that was the first generation where we enabled AVX512 for all workloads.

Earw0rm 2y ago

Depending on which CPU category. I think Intel HEDT stops at Cascade Lake, which is essentially Skylake-X Refresh from 2019? Whereas AMD has full-fat AVX512 even in gaming laptop CPUs.

deleted 2y ago

[deleted]