The RISC-V core designs that have emerged so far don't have nearly the amount of silicon dedicated to optimizing IPC as one sees in ARM, x86 and others: predict

The RISC-V core designs that have emerged so far don't have nearly the amount of silicon dedicated to optimizing IPC as one sees in ARM, x86 and others: predictors, sophisticated caches, complex instruction dispatch, deep pipelines, etc. That stuff isn't provided with the RISC-V core designs you get for free or license at low cost, because it's fabulously expensive to develop, tied to the ISA and core designs for which it is created, and jealously guarded through IP law. Will RISC-V get there eventually? People like Jim Keller are building companies around that goal. However, it will likely take years, at least, for RISC-V to approach parity.