Maybe, but it's not like the T1 or T2 had been successful designs. Idea 4x (or even 8x) SMT to hide L2 (and to an extend L3) like cache latency from an in-order

Maybe, but it's not like the T1 or T2 had been successful designs. Idea 4x (or even 8x) SMT to hide L2 (and to an extend L3) like cache latency from an in-order architecture feels didn't work out. Not many users have only parallelizable integer workloads. I suspect Sun got desperately tried to do what they could on their dwindling budget within the constraints of 64 bit SPARC. It's massive architectural register file and fixed sized register windows had to be pain to implement in an out of order uarch. I would love to gain more insight into how Fujitsu pulled this minor miracle off as the swan song SPARC.