4 ms·

Strong disagree. The RV32E subset of the RISC-V spec is even simpler than 6502 and has good modern support in cheap microcontrollers (CH32V003 etcetera) and wid

Strong disagree. The RV32E subset of the RISC-V spec is even simpler than 6502 and has good modern support in cheap microcontrollers (CH32V003 etcetera) and widely available simulators.

musicale 2y ago
RISC-V has a simple instruction encoding, but the 6502 has 151 instructions total.
- brucehoult 2y ago
  Counting instructions is problematic. 6502 has 56 mnemonics, RV32I/RV32E has 37. But mnemonics are arbitrary. Are BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS really different instructions, or just one instruction with a field specifying the condition. If you look at 8080 and Z80 assembly languages you see the same binary instructions represented with different mnemonics and some things that have different mnemonics in one are the same mnemonic with different arguments in the other. 6502, original, has 151 of the 256 eight bit opcodes used, but when you add in the immediate data or address it has millions of possible instructions: with ABS ABS,X ABS,Y modes: ADC, AND, CMP, EOR, LDA, ORA, SBC, STA with ABS ABS,X modes: ASL, DEC, INC, LDX (act ABS,Y), LDY, LSR, ROL, ROR with ABS mode: BIT, CPX, CPY, JMP, JSR, STX, STY So that's (38 + 28 + 7) * 65536 = 3,080,192 instructions right there. Immediate and the various Zero Page instructions add another few thousand. Similarly with RISC-V RV32I when you fill in the Rd, Rs1, Rs2 fields and immediates/offsets there are again many millions of possible instructions.
  - musicale 2y ago
    Maybe it's just me, but I consider data "data" and addresses "addresses" rather than instructions. I do understand your point, and I'm fine with saying there are 151 opcodes/instructions.
    - brucehoult 2y ago
      Do you consider binary code patterns that do exactly the same thing except for using different register(s) to be the same or different instructions? For example, on RISC-V `sub Rd,Rs1,Rs2` has no immediate data or addresses but can have 32768 different results on the machine state (less the 1024 with Rd = x0, and I guess the same number with Rs1 = Rs2)

Strong disagree. The RV32E subset of the RISC-V spec is even simpler than 6502 and has good modern support in cheap microcontrollers (CH32V003 etcetera) and widely available simulators.

musicale 2y ago

RISC-V has a simple instruction encoding, but the 6502 has 151 instructions total.

brucehoult 2y ago
Counting instructions is problematic. 6502 has 56 mnemonics, RV32I/RV32E has 37. But mnemonics are arbitrary. Are BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS really different instructions, or just one instruction with a field specifying the condition. If you look at 8080 and Z80 assembly languages you see the same binary instructions represented with different mnemonics and some things that have different mnemonics in one are the same mnemonic with different arguments in the other. 6502, original, has 151 of the 256 eight bit opcodes used, but when you add in the immediate data or address it has millions of possible instructions: with ABS ABS,X ABS,Y modes: ADC, AND, CMP, EOR, LDA, ORA, SBC, STA with ABS ABS,X modes: ASL, DEC, INC, LDX (act ABS,Y), LDY, LSR, ROL, ROR with ABS mode: BIT, CPX, CPY, JMP, JSR, STX, STY So that's (38 + 28 + 7) * 65536 = 3,080,192 instructions right there. Immediate and the various Zero Page instructions add another few thousand. Similarly with RISC-V RV32I when you fill in the Rd, Rs1, Rs2 fields and immediates/offsets there are again many millions of possible instructions.
- musicale 2y ago
  Maybe it's just me, but I consider data "data" and addresses "addresses" rather than instructions. I do understand your point, and I'm fine with saying there are 151 opcodes/instructions.
  - brucehoult 2y ago
    Do you consider binary code patterns that do exactly the same thing except for using different register(s) to be the same or different instructions? For example, on RISC-V `sub Rd,Rs1,Rs2` has no immediate data or addresses but can have 32768 different results on the machine state (less the 1024 with Rd = x0, and I guess the same number with Rs1 = Rs2)