I did a 16 bit processor that is compatible with RISC-V at the assembly language level but has its own binary encoding: https://github.com/jeceljr/digitalCPUzo

I did a 16 bit processor that is compatible with RISC-V at the assembly language level but has its own binary encoding: https://github.com/jeceljr/digitalCPUzoo/tree/main/drv16 https://github.com/jeceljr/digitalCPUzoo/tree/main/drv16 It is meant as a helper processor in larger FPGA projects. These need less than 64KB of memory. drv16 is about the same size as the tiniest RISC-V (SERV, Glacial) without the huge performance penalties these have.