> That is for the old 910B which was fabbed on TSMC. The rumors I have seen is that 910C is a chiplet design. Yes. As written, the (Virtuvian) AI processor CH

> That is for the old 910B which was fabbed on TSMC. The rumors I have seen is that 910C is a chiplet design. Yes. As written, the (Virtuvian) AI processor CHIPLET of Ascend 910 with TSMC N7+ process has a size of 456.25mm², >4x larger than the whole Kirin SoC. Rumor is that 910C was aimed to not redesign them significantly compared to the 910B iteration but double the amount of those AI chiplets in one package. - > What you can do is look at objective indicators such as what gets sold (phones, computers) where (China, outside China). And prices and availability of Chinese cloud computing and AI products. The size of the chiplet in the comparable TSMC N7+ process is objectively known, the size of the Kirin 9000s SoC die is objectively known. Those are good indicators that the commercial volume of the mass-produced die (Kirin) doesn't tell you much about the potential yield for the 4x larger AI-chiplet (Ascend 910 Virtuvian)