As long as it looks vaguely like any other register based ISAs, generally there is very little in an architecture that would prevent making an high performance

As long as it looks vaguely like any other register based ISAs, generally there is very little in an architecture that would prevent making an high performance implementation. Some details might make it more difficult, but Intel has shown very effectively that with enough thrust even pigs can fly. The details would be in the microarchitecture, which would not be specified by RISC-V.