5 ms·
Might be interesting to see this combined with vex. Also nice to see the recognition that memory bandwidth is an important consideration.
by Neywiny 2y ago
Might be interesting to see this combined with vex. Also nice to see the recognition that memory bandwidth is an important consideration.
- crest 2y agoSome of the old Cray machines only cached instructions and scalar data. Instead of a vector cache they used vector scratchpad registers and plenty of interleaved memory channels to keep up with the vector ALUs. That's one part of the design space you can't go RISC-V without yet an other vendor extension.