4 ms·

In my opinion, this is bad advice. Peak currents are very much a thing! for anything powered by battery or over USB. When you connect your USB gadget, you don'

In my opinion, this is bad advice. Peak currents are very much a thing! for anything powered by battery or over USB. When you connect your USB gadget, you don't want it to exceed the USB spec and fry your USB port (or USB hub). That means there is a limit to how much in total capacitance your USB gadget can have before the power surge of connecting its cable becomes an issue. And that means you usually need to use the smallest caps that are OK to do the job. You typically need to use multiple decoupling caps all over the board, so using one that is too large very quickly adds up. That's how you end up using 100nF instead of 1uF. Also, the article complains that 100nF caps have their filtering peak at the wrong frequency, but I'd argue that 20MHz to 40MHz is exactly in line with the rise and fall times of modern ICs, meaning that 100nF caps would even work better than 1uF for those ICs. As an example, look at the PCM5242 datasheet which suggests 100nF caps and their switching times are in the 16ns to 20ns range. Looking at the "impedance plot" in the original article, that means the red line is most suitable ... which is the 100nF 0402 capacitor. The article would be correct if you are working on things using old (slow) ICs and a dedicated power supply. But if you're working on USB power with modern ICs, I believe going from 100nF to 1uF is a step in the wrong direction.

robotresearcher 2y ago
The article says: "If you have a lot of devices powered off a single rail, placing lots of high-value decoupling capacitors will add up, so pay attention to inrush current. If you’re sticking 10uF decoupling caps on 20 devices then that’s 200uF. Maybe dial it back a smidge."
- fxtentacle 2y ago
  In the recommended application circuit for a PCM5242RHB DA with a TPA6120A2 headphone amp, I already count 22 decoupling caps. Adding a STM32F446 CPU adds another 21 decoupling caps. So if I was following the advice in the article, that would be 43uF of total capacitance just for a small CPU and headphone sound output. At about 10uF at 5V, you're running into issues with the USB spec. (When not using power delivery negotiation, which necessitates additional components and beefy MOSFETs) So while the article mentions that too much capacitance can be an issue, following the advice in the article will pretty much make sure you run into exactly that issue.
  - bradfa 2y ago
    But such a board likely would have a buck converter between the USB 5V input and those components and their capacitors. Just use a buck with soft start and that can effectively hide the bulk capacitance from an inrush perspective, no? Then you only count inrush for what’s in front of the buck, which won’t be nothing but can be easily controlled and designed to meet the inrush spec.
    - indrora 2y ago
      Plenty of designs are going to not use a traditional buck converter and instead use something cheap and easy like the AMS1117-33 to just linear-regulate their way to "it works good enough" for everything under 1A.
      - IX-103 2y ago
        These days switching regulator have gotten so cheap that I'm surprised someone would use a linear regulator instead. You'd probably spend more handling the extra heat than you'd save on a better regulator.
      - kevin_thibedeau 2y ago
        Modern USB requires you obey the 150 mA limit before enumeration. You are supposed to be switching power to the rest of the device that needs to exceed that limit.
- deleted 2y ago
  [deleted]
bunnie 2y ago
I'm glad I'm not the only one who was weirded out by the glossing over of the "it's better in the 20-40MHz range, I guess?" punch line. That's kind of exactly the frequency band where you need the reinforcement. The article does get it right that you need to reduce the parasitic elements to the chip, but you have to consider like, everything - not just the wires to the package, but also the lead frame, bond wires, the wiring in the chip. Usually the chip designers modeled that all out and they put decoupling capacitors on chip and did PCB model simulations that includes some specific assumption about the impedance curves of the off-chip caps, and they probably used 0.1uF in their simulations. If anything, you need closely placed decaps to prop up higher frequencies, not lower frequencies. Remember if you have a SPI bus clocking at 25MHz, 25MHz is just the fundamental - you have the whole fourier series going up to 100's of MHz on the edge. The answer I had always seen looking at the chip models is that there is an off-chip capacitance value below which it does not make sense to use because the bond wires effectively isolate the chip above certain frequencies (i.e., while smaller value capacitors have higher SRF it doesn't matter because the chip can't "see" the capacitor due to the bond wires screening it out). If you knew where that roll-off was, and you knew the curve of your capacitors + board parasitics, you'd place a cap as close as you can to the chip in the frequency band right below the roll off of the bond wires to prop up that zone. Then, you'd place larger caps farther away because, as the article notes, the inductance goes up but also you're just looking to prop up the higher impedance-at-lower-frequencies curve of the tiny cap that's close to the chip. So a lot of it depends on the exact chip you're working with and how well designed it is. A classic chip design team would have an expert who did all the parasitic modeling of the package, board, and then they'd do a noise analysis on the chip and recommend a minimum on-chip decap so the board designers don't have to worry too much, they can get away with "almost anything" in the 0.1uF range. Unfortunately chip design teams are getting leaner and leaner these days and I don't see the same level of care being put into chips. I think we more or less get away with it because there is so much margin in the chip timing; also modern chips are "mostly" (>50%) fill cells -- e.g. decoupling capacitors -- that are placed right up against the logic gates so you can get away with bloody murder on the package and power distribution networks (background: modern chips are wiring-limited, not transistor-limited, but for process stability reasons you still need to make transistors everywhere at a uniform density, so they instantiate dummy transistors that are wired as capacitors between power and ground). Where it really starts to matter is if you had e.g. a PLL and you're trying to reduce noise that the loop filter can't get rid of and in those cases often times you need much smaller capacitors because they have much better performance at higher frequencies. Yes, they suck at low frequencies - but your noise problem isn't in the 1MHz band anyways; the loop filter can track that out. It's going to be in the 100MHz+ range. And as someone noted elsewhere, in-rush current is a real problem, and too much capacitance can cause a problem for regulator stability; especially the extremely high performance ceramics. And, if you're doing an extremely power efficient design you may need to consider factors like leakage and losses due to CV-energy cycling if you shut down significant portions of the design when not in use. (edits for clarity)
Zardoz84 2y ago
Interesting... My father, was a electronics engineer, was putting always 100nF decoupling caps in his boards. And was stuff that not was powered by a USB. It was on industrial control boards. Boards controling electrovalvs and circuits in high tension AC (10-20KV) at around 10KHz to drive ozone generators. And never had issues with electrical noise in his boards.
formerly_proven 2y ago
For pluggable power there are some other considerations you shouldn't neglect, like accidentally building a decent-ish-Q series LC with the input capacitors: https://www.analog.com/media/en/technical-documentation/application-notes/an88f.pdf https://www.analog.com/media/en/technical-documentation/appl... USB-C sorta solves this because it starts at 5 V and steps up after being plugged in, but then you have issues with arcing on unplugging (see: USB-C connector spec, one of the last appendices deals with this).
MegaDeKay 2y ago
What I didn't like about the article is that he picks a couple 1 uF capacitors that he knows have good specs and then adds to the graph some random 0.1 uF cap without any specs or part numbers. How do we know this is apples to apples? We don't. It is almost like he ran out of time to write the article when he got near the end. Too bad.
timerol 2y ago
> There are two cases where I would recommend caution: > 1. If you have a lot of devices powered off a single rail, placing lots of high-value decoupling capacitors will add up, so pay attention to inrush current. If you’re sticking 10uF decoupling caps on 20 devices then that’s 200uF. Maybe dial it back a smidge. The conclusion of the article specifically mentions inrush concerns as one of the reasons to use large values. For the notch itself, relying on the difference between 0.05 Ohm and 0.02 Ohm decoupling is gonna make for a bad time, especially given how much that notch will move across DC bias and temperature.

robotresearcher 2y ago

The article says: "If you have a lot of devices powered off a single rail, placing lots of high-value decoupling capacitors will add up, so pay attention to inrush current. If you’re sticking 10uF decoupling caps on 20 devices then that’s 200uF. Maybe dial it back a smidge."

fxtentacle 2y ago
In the recommended application circuit for a PCM5242RHB DA with a TPA6120A2 headphone amp, I already count 22 decoupling caps. Adding a STM32F446 CPU adds another 21 decoupling caps. So if I was following the advice in the article, that would be 43uF of total capacitance just for a small CPU and headphone sound output. At about 10uF at 5V, you're running into issues with the USB spec. (When not using power delivery negotiation, which necessitates additional components and beefy MOSFETs) So while the article mentions that too much capacitance can be an issue, following the advice in the article will pretty much make sure you run into exactly that issue.
- bradfa 2y ago
  But such a board likely would have a buck converter between the USB 5V input and those components and their capacitors. Just use a buck with soft start and that can effectively hide the bulk capacitance from an inrush perspective, no? Then you only count inrush for what’s in front of the buck, which won’t be nothing but can be easily controlled and designed to meet the inrush spec.
  - indrora 2y ago
    Plenty of designs are going to not use a traditional buck converter and instead use something cheap and easy like the AMS1117-33 to just linear-regulate their way to "it works good enough" for everything under 1A.
    - IX-103 2y ago
      These days switching regulator have gotten so cheap that I'm surprised someone would use a linear regulator instead. You'd probably spend more handling the extra heat than you'd save on a better regulator.
    - kevin_thibedeau 2y ago
      Modern USB requires you obey the 150 mA limit before enumeration. You are supposed to be switching power to the rest of the device that needs to exceed that limit.
deleted 2y ago
[deleted]

bunnie 2y ago

I'm glad I'm not the only one who was weirded out by the glossing over of the "it's better in the 20-40MHz range, I guess?" punch line. That's kind of exactly the frequency band where you need the reinforcement. The article does get it right that you need to reduce the parasitic elements to the chip, but you have to consider like, everything - not just the wires to the package, but also the lead frame, bond wires, the wiring in the chip. Usually the chip designers modeled that all out and they put decoupling capacitors on chip and did PCB model simulations that includes some specific assumption about the impedance curves of the off-chip caps, and they probably used 0.1uF in their simulations. If anything, you need closely placed decaps to prop up higher frequencies, not lower frequencies. Remember if you have a SPI bus clocking at 25MHz, 25MHz is just the fundamental - you have the whole fourier series going up to 100's of MHz on the edge. The answer I had always seen looking at the chip models is that there is an off-chip capacitance value below which it does not make sense to use because the bond wires effectively isolate the chip above certain frequencies (i.e., while smaller value capacitors have higher SRF it doesn't matter because the chip can't "see" the capacitor due to the bond wires screening it out). If you knew where that roll-off was, and you knew the curve of your capacitors + board parasitics, you'd place a cap as close as you can to the chip in the frequency band right below the roll off of the bond wires to prop up that zone. Then, you'd place larger caps farther away because, as the article notes, the inductance goes up but also you're just looking to prop up the higher impedance-at-lower-frequencies curve of the tiny cap that's close to the chip. So a lot of it depends on the exact chip you're working with and how well designed it is. A classic chip design team would have an expert who did all the parasitic modeling of the package, board, and then they'd do a noise analysis on the chip and recommend a minimum on-chip decap so the board designers don't have to worry too much, they can get away with "almost anything" in the 0.1uF range. Unfortunately chip design teams are getting leaner and leaner these days and I don't see the same level of care being put into chips. I think we more or less get away with it because there is so much margin in the chip timing; also modern chips are "mostly" (>50%) fill cells -- e.g. decoupling capacitors -- that are placed right up against the logic gates so you can get away with bloody murder on the package and power distribution networks (background: modern chips are wiring-limited, not transistor-limited, but for process stability reasons you still need to make transistors everywhere at a uniform density, so they instantiate dummy transistors that are wired as capacitors between power and ground). Where it really starts to matter is if you had e.g. a PLL and you're trying to reduce noise that the loop filter can't get rid of and in those cases often times you need much smaller capacitors because they have much better performance at higher frequencies. Yes, they suck at low frequencies - but your noise problem isn't in the 1MHz band anyways; the loop filter can track that out. It's going to be in the 100MHz+ range. And as someone noted elsewhere, in-rush current is a real problem, and too much capacitance can cause a problem for regulator stability; especially the extremely high performance ceramics. And, if you're doing an extremely power efficient design you may need to consider factors like leakage and losses due to CV-energy cycling if you shut down significant portions of the design when not in use. (edits for clarity)

Zardoz84 2y ago

Interesting... My father, was a electronics engineer, was putting always 100nF decoupling caps in his boards. And was stuff that not was powered by a USB. It was on industrial control boards. Boards controling electrovalvs and circuits in high tension AC (10-20KV) at around 10KHz to drive ozone generators. And never had issues with electrical noise in his boards.

formerly_proven 2y ago

For pluggable power there are some other considerations you shouldn't neglect, like accidentally building a decent-ish-Q series LC with the input capacitors: https://www.analog.com/media/en/technical-documentation/application-notes/an88f.pdf https://www.analog.com/media/en/technical-documentation/appl... USB-C sorta solves this because it starts at 5 V and steps up after being plugged in, but then you have issues with arcing on unplugging (see: USB-C connector spec, one of the last appendices deals with this).

MegaDeKay 2y ago

What I didn't like about the article is that he picks a couple 1 uF capacitors that he knows have good specs and then adds to the graph some random 0.1 uF cap without any specs or part numbers. How do we know this is apples to apples? We don't. It is almost like he ran out of time to write the article when he got near the end. Too bad.

timerol 2y ago

> There are two cases where I would recommend caution: > 1. If you have a lot of devices powered off a single rail, placing lots of high-value decoupling capacitors will add up, so pay attention to inrush current. If you’re sticking 10uF decoupling caps on 20 devices then that’s 200uF. Maybe dial it back a smidge. The conclusion of the article specifically mentions inrush concerns as one of the reasons to use large values. For the notch itself, relying on the difference between 0.05 Ohm and 0.02 Ohm decoupling is gonna make for a bad time, especially given how much that notch will move across DC bias and temperature.