4 ms·
I've missed the stories on this until now. Is it known (and is there an ELI5) how they were able to do it so much more efficiently?
by zeven7 2y ago
I've missed the stories on this until now. Is it known (and is there an ELI5) how they were able to do it so much more efficiently?
- riffraff 2y agoIIUC they released a paper, it's partially algorithmic improvements partially good old low level optimization.
- CursedSilicon 2y agoThere's something to be said about the idea that instead of just dumping oceans of money into buying Nvidia cards they just...optimized what they had I'd say the wider industry could learn a thing or two, but as other commentors have joked. The line must go up
- Neonlicht 2y agoAh but why care about efficiency when you have basically unlimited investor money? Reminds me of Japanese cars and the OPEC boycott in the 1970s...
- plussed_reader 2y agoThe double edged sword of export controls.
- mnky9800n 2y agoCreativity always delivers when minds are constrained.
- plussed_reader 2y agoIs that what we can call Project2025? Creativity from constrained minds?
- mnky9800n 2y agosurely more relevant comments could exist in the aether of the internet.
- plussed_reader 2y agoYour reply doesn't read like a refute to me, mnky9800n.
- rx_tx 2y agoThis article has good background, context, and explanations [1] They skipped CUDA and instead used PTX which is a lower level instruction set where they were able to implement more performant cross-chip comms to make up for the less-performant H800 chips. [1]: https://stratechery.com/2025/deepseek-faq/ https://stratechery.com/2025/deepseek-faq/
- yread 2y agoSo can people do the same in SPIR for OpenCL or amdgcn? https://en.wikipedia.org/wiki/Standard_Portable_Intermediate_Representation https://en.wikipedia.org/wiki/Standard_Portable_Intermediate... https://www.khronos.org/spir/ https://www.khronos.org/spir/ Or even better in the unified language like SYCL? https://cdrdv2-public.intel.com/786536/Heidelberg_IWOCL__SYCLCon_2023_paper_2566-1.pdf https://cdrdv2-public.intel.com/786536/Heidelberg_IWOCL__SYC...
- saagarjha 2y ago> Moreover, if you actually did the math on the previous question, you would realize that DeepSeek actually had an excess of computing; that’s because DeepSeek actually programmed 20 of the 132 processing units on each H800 specifically to manage cross-chip communications. This is actually impossible to do in CUDA. You can do this just fine in CUDA, no PTX required. Of course all the major shops are using inline PTX at the very least to access the Tensor cores effectively.