3 ms·

bah - Team Stratus!! None of this wanna be software redundancy - real computers do it hardware !! /jk Always was a bit of rivalry between them (at least with

bah - Team Stratus!! None of this wanna be software redundancy - real computers do it hardware !! /jk Always was a bit of rivalry between them (at least with Wall St. data centers)

sillywalk 2y ago
They still kept their software redundancy, but when Tandem switched from their own custom CPUs to MIPS, they used pairs of lock-stepped CPUs like Stratus. When they still had their own multi-board proprietary processors, Tandem also used lock-stepped microprocessors in their maintenance and diagnostic subsytem and some of their communications controllers. I also gather Stratus is still around running on x86-64.
- schoen 2y ago
  Do you know (or does anyone else reading this know) how the lock-stepping works? It seems like it would be an enormous challenge to keep modern CPUs exactly in lockstep. All of the same interrupts have to occur at exactly the same times and be handled in the same amount of time? (I guess the hardware has to physically ensure that every interrupt is raised on both CPUs at the same time?)
  - sillywalk 2y ago
    I believe, but am not sure, that NonStop ditched lock-stepping altogether for their NonStop Multicore Architecture when Itanium went multicore, but I can't find a paper on it, or their current X86-64 Architecture. They used a custom chipset that compared the two MIPS processors and also synchronized them on external interrupts. I believe that Tandem System Review is on archive.org. Volume 8, Number 1 (Spring 92) has info on the first generation lock-stepped TNS/R, and Volume 10, Number 1 (January 94) has info on the 2nd generation MIPS "Himalaya K1000". For Itanium, the processors were loosely synchronized, but not really lockstepped. They ran the same application code, but the processors could have different cache, TLB hits, etc. They got synchronized on external IO, all of which went over the ServerNet. There is a paper called NonStop® Advanced Architecture[0] by David Bernick, et. al that has the details on their 1st generation Itanium systems. [0] https://www.cse.chalmers.se/edu/year/2012/course/ZZ_courses_2011/EDA122/course-material-2011/Hp_non_stop.pdf https://www.cse.chalmers.se/edu/year/2012/course/ZZ_courses_... (the only source I could find that had the paper)
- mech422 2y ago
  Oh? I didn't realize they used hardware level on MIPS Stratus was pretty nice - I liked VOS :-)

bah - Team Stratus!! None of this wanna be software redundancy - real computers do it hardware !! /jk Always was a bit of rivalry between them (at least with Wall St. data centers)

sillywalk 2y ago

They still kept their software redundancy, but when Tandem switched from their own custom CPUs to MIPS, they used pairs of lock-stepped CPUs like Stratus. When they still had their own multi-board proprietary processors, Tandem also used lock-stepped microprocessors in their maintenance and diagnostic subsytem and some of their communications controllers. I also gather Stratus is still around running on x86-64.

schoen 2y ago
Do you know (or does anyone else reading this know) how the lock-stepping works? It seems like it would be an enormous challenge to keep modern CPUs exactly in lockstep. All of the same interrupts have to occur at exactly the same times and be handled in the same amount of time? (I guess the hardware has to physically ensure that every interrupt is raised on both CPUs at the same time?)
- sillywalk 2y ago
  I believe, but am not sure, that NonStop ditched lock-stepping altogether for their NonStop Multicore Architecture when Itanium went multicore, but I can't find a paper on it, or their current X86-64 Architecture. They used a custom chipset that compared the two MIPS processors and also synchronized them on external interrupts. I believe that Tandem System Review is on archive.org. Volume 8, Number 1 (Spring 92) has info on the first generation lock-stepped TNS/R, and Volume 10, Number 1 (January 94) has info on the 2nd generation MIPS "Himalaya K1000". For Itanium, the processors were loosely synchronized, but not really lockstepped. They ran the same application code, but the processors could have different cache, TLB hits, etc. They got synchronized on external IO, all of which went over the ServerNet. There is a paper called NonStop® Advanced Architecture[0] by David Bernick, et. al that has the details on their 1st generation Itanium systems. [0] https://www.cse.chalmers.se/edu/year/2012/course/ZZ_courses_2011/EDA122/course-material-2011/Hp_non_stop.pdf https://www.cse.chalmers.se/edu/year/2012/course/ZZ_courses_... (the only source I could find that had the paper)
mech422 2y ago
Oh? I didn't realize they used hardware level on MIPS Stratus was pretty nice - I liked VOS :-)