> I'm not sure this makes sense as proposed. Where is the CPU going to put these pre-decoded instructions? I don't know what folks do now, but Intel had a trac

> I'm not sure this makes sense as proposed. Where is the CPU going to put these pre-decoded instructions? I don't know what folks do now, but Intel had a trace cache as of a few years ago. That trace cache contains decoded instructions. > What would make sense (to me at least) is if you could have an instruction that tells the branch predictor "the branch at address X will most likely jump to address Y next time." US Patent 5,949,995 .