3 ms·
I can't seem to find a reference at the moment. I think I saw a talk on this years ago. The idea is that the circuit complexity of adders is high because of ca
by andrewla 2y ago
I can't seem to find a reference at the moment.
I think I saw a talk on this years ago. The idea is that the circuit complexity of adders is high because of carry cascade but since Gray codes only ever flip a single bit on increments, then a Gray code counter can be made very simple and have no glitch states. Might have showed up in the context of asynchronous VLSI designs.
- variaga 2y agoSpeaking as a digital HW designer, Gray counters (where you only ever calculate 'x+1' are actually slightly more complicated than normal binary counters, and general Gray code addition (calculate 'x+y' for arbitrary x,y) is significantly more complicated (to the extent that I've never actually seen it done in 28 years of practice - everyone figures out a way to move addition to binary values instead). You are correct that Gray counters only ever toggle one bit at a time and have no 'glitch' states in the sense that an asynchronous counter will always capture either 'x' or 'x+1' (can't be sure which), but not any other value. This is commonly used to pass e.g. FIFO pointers (or modular counters, generally) between asynchronous clock domains. The problem is, Gray codes (the standard, symmetric gray code, that is - there are multiple possible gray codes, but the non-standard ones are worse) are not a purely positional encoding as defined in the article. - With a binary encoding, for all 'N' if bit N is set, you add 2^N to the calculated value. - With a Gray encoding, for all N if (bit N XOR bit N+1) is set, you add 2^N to the calculated value - the encoding of each power of 2 is spread across 2 bits.