From that link: "Really what x86 needs is a PREDECODE instruction, a code equivalent of the PREFETCH data instruction, which takes a code pointer as an operand

From that link: "Really what x86 needs is a PREDECODE instruction, a code equivalent of the PREFETCH data instruction, which takes a code pointer as an operand and hints to the CPU that it should start decoding that code." I'm not sure this makes sense as proposed. Where is the CPU going to put these pre-decoded instructions? The instruction decoder is the first stage of a pipeline, and the decoded instructions are usually fed directly to subsequent pipeline stages. When a branch is predicted, the stream of instructions continues to be decoded and executed in program order from the predicted branch target, and the pipeline stays full. But you can't use this "PREDECODE" instruction to keep the pipeline full, because you can't speculatively execute instructions unless you have already executed all of their dependent instructions (ie. all the instructions prior to the branch that will jump to the target we are feeing to PREDECODE). What would make sense (to me at least) is if you could have an instruction that tells the branch predictor "the branch at address X will most likely jump to address Y next time." The predictor could then update its tables to adjust the prediction it will make. It seems like this should be pretty straightforward; since the branch predictor and instruction decoder both live at the head of the pipeline, there shouldn't be any danger that the hint is registered only after the branch has already been predicted.