For anyone interested in a "not-so-simple" CPU design, I have a couple old college assignments from a CPU design class that may be fun to peruse: This one is a

For anyone interested in a "not-so-simple" CPU design, I have a couple old college assignments from a CPU design class that may be fun to peruse: This one is a 4-stage pipelined CPU: https://github.com/wyager/Lambda16 https://github.com/wyager/Lambda16 This one is a superscalar out-of-order CPU: https://github.com/wyager/Lambda17 https://github.com/wyager/Lambda17 Both are written in Clash, which is a subset of Haskell that compiles to target FPGAs. It's an incredibly OP HDL. I don't think I ever ran the second one on an actual FPGA, because at the time values of type `Char` wouldn't synthesize, but I think the Clash compiler fixed that at some point.