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LoongArch64 Subjective Higlights
- unwind 2y agoThis was very interesting, but is there some kind of formatting failure that prevents the actual instruction definitions (the syntax) from being shown alongside the explanations? Seemed ... oddly confusing. Even if these are undocumented "Black market" instructions, someone must have picked mnemonics?
- duskwuff 2y agoSome of the headings in the document are white and blend into the background. Click the moon icon in the upper left corner to enable dark mode and make them visible.
- deivid 2y agoNice article! Do you have a board to experiment on or is this all on QEMU? I've been wanting to try one of the Banana Pi boards, but I think it's going to be _quite_ painful
- pantalaimon 2y agoYou can get the Asus XC-LS3A6M from e.g. AliExpress. It comes with a 3A6000 CPU which is plenty fast (compared to ARM SBCs), similar to Zen 1. Alpine is one of the few western distributions that has full support for the architecture.
- sidewndr46 2y agoI wasn't aware of this. It looks pretty neat. But the price point I'm seeing is more than $400 US. So I'm not sure it is price competitive yet
- snvzz 2y agoThe RISC-V Vector article[0] on the same site is quite interesting as well. 0. http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.htm...
- Joker_vD 2y agoWoah, what an array of varied and sometimes indispensable instructions. Does it all still count as RISC?
- deleted 2y ago[deleted]
- Pet_Ant 2y agoAs I've been studying the history of CPUs I'm not so sure that RISC really makes sense to talk about outside of the original period it was created. It was a belief that at the point it time that repurposing the budget allocated to decoding complex instructions and the was better spent on more register & cache, and allowing operations to clock faster due to their simplicity. Now that we have speculative execution, cracking into micro-ops and multi-issue units, it's really not RISCy at all. POWER and x86 really have more in common than they don't.
- wat10000 2y agoRight, fundamentally RISC was about aligning the instruction set with the hardware. At the hardware level, you can’t do arithmetic on a value in memory, you have to load it into a register first. CISC might still give you an add instruction that operates on memory, and behind the scenes it does load, add. RISC says, let’s just do those more basic operations, and the program can combine them. The hardware can be much simpler as a result. Now, the hardware is stupidly complex anyway and the instructions generally don’t line up too well with the underlying hardware regardless. Consider branch delay slots. Initially, this lined up well with the hardware. The branch takes extra time, so let’s expose that to the program instead of hiding it, then the hardware gets simpler and programs can take advantage of it. Trouble is, once your pipelining gets more complex than “branches take an extra cycle and we can perform another instruction in that time” then it doesn’t align with the hardware anymore. It makes things worse, since now your fancier hardware has to support this weird thing that doesn’t match how they actually operate.
- Pet_Ant 2y ago