Additional wafer area would be a marginal increase in performance (+~20% core core best case) but increases the complexity of their design, and requires they fi

Additional wafer area would be a marginal increase in performance (+~20% core core best case) but increases the complexity of their design, and requires they figure out how to package/connect/house/etc. a non-standard shape. A wafer scale chip is already a huge tech risk, why spend more novelty budget on nonessential weirdness?