5 ms·

I'm amazed. The technical wizardry involved in stuffing this into such a small area of Silicon, then simulating it in a web browser, is awe inspiring. At the s

I'm amazed. The technical wizardry involved in stuffing this into such a small area of Silicon, then simulating it in a web browser, is awe inspiring. At the same time I'm filled with doubt I can get my BitGrid to the same state.

Taniwha 2y ago
You can do it too, come on over to https://www.tinytapeout.com/ https://www.tinytapeout.com/
- hgo 2y ago
  I _need_ to tinytapout! Don't know what, don't know how, but the sense of need is tickling! I feel like twelve again in front of a 286 without a case.
- femto 2y ago
  Interesting: https://www.tinytapeout.com/competitions/demoscene-tt10/ https://www.tinytapeout.com/competitions/demoscene-tt10/ This seems to be the currently open tapeout. How low-level can you go with tinytapeout? One can imagine the insanity of doing a manual layout to push a demo to extremes.
  - sans_souse 2y ago
    Those baseball caps are BALLIN
  - Taniwha 2y ago
    You can work at the polygon level if you really want to, you can write gates and have it lay them out for you (or place them yourself), or work in a higher level language like verilog and have it compile them into gates for you (what most people do) - your choice
    - Lerc 2y ago
      How good are things like verilog at producing efficient layouts? Coming from the perspective of software. Hand coded asm can usually squeeze a lot more than a compiler into a small number of bytes, but that's mostly due to compilers targeting speed of execution instead of size.
      - gorkish 2y ago
        Verilog describes the logic. This is extremely simplified, but you can imagine that verilog and other HDLs are "compiled" into a big schematic of logic gates and a big list of signal timing constraints between them. From that schematic and constraint list, a solver then works to do place and route. Both of these intermediate stages between verilog and the final working hardware are where all of the secret sauce in semiconductor design actually lives. Both of these steps will be affected by the process target. Are you building for an FPGA or CPLD? Which one? If for an ASIC what is the process node? What logic elements are available in your node? Just like when you order a PCB, the process design rules generally come with prescribed information about the manufacturing constraints -- what works and what doesn't. And ultimately you cant rely on hand layout to throw down millions/billions of circuit elements anyway so you have to build solvers and all kinds of other mind bogglingly sophisticated automation to the party. The diminishing returns of manual optimization here should be evident; if you want to do that work, become a process design engineer. We do need more open information in this space! Tiny Tapeout is such a great project!
        Lerc 2y ago
        That's all very analogous to software compilers, but doesn't really answer the question I had. Specifically for Tiny Tapeout, how much is there to be gained by going low level? I feel like using a subset of verilog features might get you most of the way there. Consider that there is a 512 byte BASIC interpreter in asm, that's well beyond what a compiler could manage. I would expect logic expressions in verilog to get closer to a hand crafted approach than that, but I might be wrong.
        2y ago

Taniwha 2y ago

You can do it too, come on over to https://www.tinytapeout.com/ https://www.tinytapeout.com/

hgo 2y ago
I _need_ to tinytapout! Don't know what, don't know how, but the sense of need is tickling! I feel like twelve again in front of a 286 without a case.
femto 2y ago
Interesting: https://www.tinytapeout.com/competitions/demoscene-tt10/ https://www.tinytapeout.com/competitions/demoscene-tt10/ This seems to be the currently open tapeout. How low-level can you go with tinytapeout? One can imagine the insanity of doing a manual layout to push a demo to extremes.
- sans_souse 2y ago
  Those baseball caps are BALLIN
- Taniwha 2y ago
  You can work at the polygon level if you really want to, you can write gates and have it lay them out for you (or place them yourself), or work in a higher level language like verilog and have it compile them into gates for you (what most people do) - your choice
  - Lerc 2y ago
    How good are things like verilog at producing efficient layouts? Coming from the perspective of software. Hand coded asm can usually squeeze a lot more than a compiler into a small number of bytes, but that's mostly due to compilers targeting speed of execution instead of size.
    - gorkish 2y ago
      Verilog describes the logic. This is extremely simplified, but you can imagine that verilog and other HDLs are "compiled" into a big schematic of logic gates and a big list of signal timing constraints between them. From that schematic and constraint list, a solver then works to do place and route. Both of these intermediate stages between verilog and the final working hardware are where all of the secret sauce in semiconductor design actually lives. Both of these steps will be affected by the process target. Are you building for an FPGA or CPLD? Which one? If for an ASIC what is the process node? What logic elements are available in your node? Just like when you order a PCB, the process design rules generally come with prescribed information about the manufacturing constraints -- what works and what doesn't. And ultimately you cant rely on hand layout to throw down millions/billions of circuit elements anyway so you have to build solvers and all kinds of other mind bogglingly sophisticated automation to the party. The diminishing returns of manual optimization here should be evident; if you want to do that work, become a process design engineer. We do need more open information in this space! Tiny Tapeout is such a great project!
      - Lerc 2y ago
        That's all very analogous to software compilers, but doesn't really answer the question I had. Specifically for Tiny Tapeout, how much is there to be gained by going low level? I feel like using a subset of verilog features might get you most of the way there. Consider that there is a 512 byte BASIC interpreter in asm, that's well beyond what a compiler could manage. I would expect logic expressions in verilog to get closer to a hand crafted approach than that, but I might be wrong.
        2y ago